MCP6271/1R/2/3/4/5
170 µA, 2 MHz Rail-to-Rail Op Amp
Features
•
•
•
•
•
•
•
Gain Bandwidth Product: 2 MHz (typical)
Supply Current: I
Q
= 170 µA (typical)
Supply Voltage: 2.0V to 6.0V
Rail-to-Rail Input/Output
Extended Temperature Range: –40°C to +125°C
Available in Single, Dual and Quad Packages
Parts with Chip Select (CS)
- Single (MCP6273)
- Dual (MCP6275)
Description
The Microchip Technology Inc. MCP6271/1R/2/3/4/5
family of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 2 MHz
Gain Bandwidth Product (GBWP) and a 65° Phase
Margin. This family also operates from a single supply
voltage as low as 2.0V, while drawing 170 µA (typical)
quiescent current. The MCP6271/1R/2/3/4/5 supports
rail-to-rail input and output swing, with a common mode
input voltage range of V
DD
+ 300 mV to V
SS
– 300 mV.
This family of op amps is designed with Microchip’s
advanced CMOS process.
The MCP6275 has a Chip Select input (CS) for dual op
amps in an 8-pin package and is manufactured by
cascading two op amps (the output of op amp A
connected to the non-inverting input of op amp B). The
CS input puts the device in low power mode.
The MCP6271/1R/2/3/4/5 family operates over the
Extended Temperature Range of –40°C to +125°C,
with a power supply range of 2.0V to 6.0V.
Applications
•
•
•
•
•
•
Automotive
Portable Equipment
Photodiode Amplifier
Analog Filters
Notebooks and PDAs
Battery Powered Systems
Available Tools
•
•
•
•
•
•
SPICE Macro Models
FilterLab
®
Software
Mindi™ Circuit Designer & Simulator
MAPS (Microchip Advanced Part Selector)
Analog Demonstration and Evaluation Boards
Application Notes
Package Types
MCP6271
PDIP, SOIC, MSOP
NC 1
V
IN
– 2
V
IN
+ 3
V
SS
4
-
+
8 NC
7 V
DD
6 V
OUT
5 NC
V
OUT
1
V
SS
2
V
IN
+ 3
-
4 V
IN
–
+
MCP6271
SOT-23-5
5 V
DD
MCP6271R
SOT-23-5
V
OUT
1
V
DD
2
V
IN
+ 3
-
4 V
IN
–
+
5 V
SS
MCP6272
PDIP, SOIC, MSOP
V
OUTA
1
V
INA
– 2
V
INA
+ 3
V
SS
4
- +
+ -
8 V
DD
7 V
OUTB
6 V
INB
–
5 V
INB
+
MCP6273
PDIP, SOIC, MSOP
NC 1
V
IN
– 2
V
IN
+ 3
V
SS
4
-
+
8 CS
7 V
DD
5 NC
V
OUT
1
V
SS
2
MCP6273
SOT-23-6
MCP6274
PDIP, SOIC, TSSOP
6 V
DD
V
OUTA
1
MCP6275
PDIP, SOIC, MSOP
8 V
DD
- +
+ -
14 V
OUTD
V
OUTA
/V
INB
+ 1
- + + - 13 V
IND
–
12 V
IND
+
11 V
SS
10 V
INC
+
-+ +- 9 V –
INC
8 V
OUTC
V
INA
– 2
V
INA
+ 3
V
SS
4
-
5 CS
V
INA
– 2
V
DD
4
V
INB
+ 5
V
INB
– 6
V
OUTB
7
7 V
OUTB
6 V
INB
–
5 CS
+
6 V
OUT
V
IN
+ 3
4 V
IN
– V
INA
+ 3
©
2008 Microchip Technology Inc.
DS21810F-page 1
MCP6271/1R/2/3/4/5
1.0
ELECTRICAL
CHARACTERISTICS
† Notice:
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
††
See
Section 4.1.2 “Input Voltage and Current Limits”.
Absolute Maximum Ratings †
V
DD
– V
SS
........................................................................7.0V
Current at Input Pins ....................................................±2 mA
Analog Inputs (V
IN
+ and V
IN
–) †† .. V
SS
– 1.0V to V
DD
+ 1.0V
All other Inputs and Outputs .......... V
SS
– 0.3V to V
DD
+ 0.3V
Difference Input Voltage ...................................... |V
DD
– V
SS
|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Junction Temperature (T
J
) . .........................................+150°C
ESD Protection On All Pins (HBM/MM)
................ ≥
4 kV/400V
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2,
V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 10 kΩ to V
L
and CS is tied low. (Refer to
Figure 1-2
and
Figure 1-3).
Parameters
Input Offset (Note 1)
Input Offset Voltage
Input Offset Voltage
(Extended Temperature)
Input Offset Temperature Drift
Power Supply Rejection Ratio
Input Bias Current and Impedance
Input Bias Current
At Temperature
At Temperature
Input Offset Current
Common Mode Input Impedance
Differential Input Impedance
Common Mode (Note 4)
Common Mode Input Voltage Range
Common Mode Rejection Ratio
Common Mode Rejection Ratio
Open-Loop Gain
DC Open-Loop Gain (Large Signal)
Note 1:
2:
3:
4:
A
OL
90
110
—
dB
V
OUT
= 0.2V to V
DD
– 0.2V,
V
CM
= V
SS
(Note 1)
V
CMR
V
CMR
CMRR
CMRR
V
SS
−
0.15
V
SS
−
0.30
70
65
—
—
85
80
V
DD
+ 0.15
V
DD
+ 0.30
—
—
V
V
dB
dB
V
DD
= 2.0V
(Note 5)
V
DD
= 5.5V
(Note 5)
V
CM
= –0.3V to 2.5V, V
DD
= 5V
(Note 6)
V
CM
= –0.3V to 5.3V, V
DD
= 5V
(Note 6)
I
B
I
B
I
B
I
OS
Z
CM
Z
DIFF
—
—
—
—
—
—
±1.0
50
2
±1.0
10 ||6
10
13
||3
13
Sym
Min
Typ
Max
Units
Conditions
V
OS
V
OS
ΔV
OS
/ΔT
A
PSRR
–3.0
–5.0
—
70
—
—
±1.7
90
+3.0
+5.0
—
—
—
200
5
—
—
—
mV
mV
V
CM
= V
SS
T
A
= –40°C to +125°C, V
CM
= V
SS
µV/°C T
A
= –40°C to +125°C, V
CM
= V
SS
dB
pA
pA
nA
pA
V
CM
= V
SS
Note 2
T
A
= +85°C
(Note 2)
T
A
= +125°C
(Note 2)
Note 3
Ω||pF
Note 3
Ω||pF
Note 3
5:
6:
7:
The MCP6275’s V
CM
for op amp B (pins V
OUTA
/V
INB
+ and V
INB
–) is V
SS
+ 100 mV.
The current at the MCP6275’s V
INB
– pin is specified by I
B
only.
This specification does not apply to the MCP6275’s V
OUTA
/V
INB
+ pin.
The MCP6275’s V
INB
– pin (op amp B) has a common mode input voltage range (V
CMR
) of V
SS
+ 100 mV to
V
DD
– 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s V
OUTA
/V
INB
+ pin (op amp B)
has a voltage range specified by V
OH
and V
OL
.
Set by design and characterization.
Does not apply to op amp B of the MCP6275.
All parts with date codes November 2007 and later have been screened to ensure operation at V
DD
= 6.0V. However,
the other minimum and maximum specifications are measured at 2.0V and 5.5V.
DS21810F-page 2
©
2008 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2,
V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 10 kΩ to V
L
and CS is tied low. (Refer to
Figure 1-2
and
Figure 1-3).
Parameters
Output
Maximum Output Voltage Swing
Output Short Circuit Current
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note 1:
2:
3:
4:
V
DD
I
Q
2.0
100
—
170
6.0
240
V
µA
I
O
= 0
V
OL
, V
OH
I
SC
V
SS
+ 15
—
—
±25
V
DD
−
15
—
mV
mA
0.5V input overdrive
(Note 4)
Sym
Min
Typ
Max
Units
Conditions
5:
6:
7:
The MCP6275’s V
CM
for op amp B (pins V
OUTA
/V
INB
+ and V
INB
–) is V
SS
+ 100 mV.
The current at the MCP6275’s V
INB
– pin is specified by I
B
only.
This specification does not apply to the MCP6275’s V
OUTA
/V
INB
+ pin.
The MCP6275’s V
INB
– pin (op amp B) has a common mode input voltage range (V
CMR
) of V
SS
+ 100 mV to
V
DD
– 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s V
OUTA
/V
INB
+ pin (op amp B)
has a voltage range specified by V
OH
and V
OL
.
Set by design and characterization.
Does not apply to op amp B of the MCP6275.
All parts with date codes November 2007 and later have been screened to ensure operation at V
DD
= 6.0V. However,
the other minimum and maximum specifications are measured at 2.0V and 5.5V.
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2,
V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 10 kΩ to V
L
, C
L
= 60 pF and CS is tied low. (Refer to
Figure 1-2
and
Figure 1-3).
Parameters
AC Response
Gain Bandwidth Product
Phase Margin
Slew Rate
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Sym
GBWP
PM
SR
E
ni
e
ni
i
ni
Min
—
—
—
—
—
—
Typ
2.0
65
0.9
4.6
20
3
Max
—
—
—
—
—
—
Units
MHz
°
V/µs
µV
P-P
nV/√Hz
fA/√Hz
Conditions
G = +1 V/V
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
CS
V
IL
t
ON
V
IH
t
OFF
High-Z
-0.7 µA
(typical)
0.7 µA
(typical)
V
OUT
High-Z
-0.7 µA
(typical)
I
SS
0.7 µA
(typical)
I
CS
-170 µA
(typical)
10 nA
(typical)
FIGURE 1-1:
Timing Diagram for the Chip
Select (CS) pin on the MCP6273 and MCP6275.
©
2008 Microchip Technology Inc.
DS21810F-page 3
MCP6271/1R/2/3/4/5
TEMPERATURE SPECIFICATIONS
Electrical Characteristics:
Unless otherwise indicated, V
DD
= +2.0V to +5.5V and V
SS
= GND.
Parameters
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 6L-SOT-23
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
Note:
θ
JA
θ
JA
θ
JA
θ
JA
θ
JA
θ
JA
θ
JA
θ
JA
—
—
—
—
—
—
—
—
256
230
85
163
206
70
120
100
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
T
A
T
A
T
A
–40
–40
–65
—
—
—
+125
+125
+150
°C
°C
°C
Note
Sym
Min
Typ
Max
Units
Conditions
The Junction Temperature (T
J
) must not exceed the Absolute Maximum specification of +150°C.
MCP6273/MCP6275 CHIP SELECT SPECIFICATIONS
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND,
V
CM
= V
DD
/2, V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 10 kΩ to V
DD
/2, C
L
= 60 pF and CS is tied low.
Parameters
CS Low Specifications
CS Logic Threshold, Low
CS Input Current, Low
CS High Specifications
CS Logic Threshold, High
CS Input Current, High
GND Current per Amplifier
Amplifier Output Leakage
Dynamic Specifications (Note 1)
CS Low to Valid Amplifier
Output, Turn on Time
CS High to Amplifier Output
High-Z
Hysteresis
Note 1:
t
ON
—
4
10
µs
CS Low
≤
0.2 V
DD
, G = +1 V/V,
V
IN
= V
DD
/2, V
OUT
= 0.9 V
DD
/2,
V
DD
= 5.0V
CS High
≥
0.8 V
DD
, G = +1 V/V,
V
IN
= V
DD
/2, V
OUT
= 0.1 V
DD
/2
V
DD
= 5V
V
IH
I
CSH
I
SS
—
0.8V
DD
—
—
—
—
0.7
–0.7
0.01
V
DD
2
—
—
V
µA
µA
µA
CS = V
DD
CS = V
DD
CS = V
DD
V
IL
I
CSL
V
SS
—
—
0.01
0.2V
DD
—
V
µA
CS = V
SS
Sym
Min
Typ
Max
Units
Conditions
t
OFF
V
HYST
—
—
0.01
0.6
—
—
µs
V
The input condition (V
IN
) specified applies to both op amp A and B of the MCP6275. The dynamic
specification is tested at the output of op amp B (V
OUTB
).
DS21810F-page 4
©
2008 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
1.1
Test Circuits
The test circuits used for the DC and AC tests are
shown in
Figure 1-2
and
Figure 1-3.
The bypass
capacitors are laid out according to the rules discussed
in
Section 4.7 “Supply Bypass”.
V
DD
R
N
0.1 µF 1 µF
V
OUT
C
L
V
DD
/2 R
G
R
F
V
L
R
L
V
IN
MCP627X
FIGURE 1-2:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
V
DD
R
N
0.1 µF 1 µF
V
OUT
C
L
V
IN
R
G
R
F
V
L
R
L
V
DD
/2
MCP627X
FIGURE 1-3:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
©
2008 Microchip Technology Inc.
DS21810F-page 5
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