CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
GSSF
I
GSSR
I
DSS1
I
DSS2
I
DSS3
I
AR
V
DS(ON)
r
DS(ON)
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(TH)
Q
g(ON)
Q
gM
V
GP
Q
gS
Q
gD
V
SD
t
rr
R
θJC
R
θJA
Free Air Operation
I
D
= 6A, V
GD
= 0
I = 6A; di/dt = 100A/µs
V
DD
= 50V, ID = 6A
I
GS1
= I
GS2
0
≤
V
GS
≤
20
TEST CONDITIONS
I
D
= 1mA, V
GS
= 0V
I
D
= 1mA, V
DS
= V
GS
V
GS
= +20V
V
GS
= -20V
V
DS
= 100V, V
GS
= 0
V
DS
= 80V, V
GS
= 0
V
DS
= 80V, V
GS
= 0, T
C
= 125
o
C
Time = 20µs
V
GS
= 10V, I
D
= 6A
V
GS
= 10V, I
D
= 4A
V
DD
= 50V, I
D
= 6A
Pulse Width = 3µs
Period = 300µs, Rg = 25Ω
0
≤
V
GS
≤
10 (See Test Circuit)
MIN
100
2.0
-
-
-
-
-
-
-
-
-
-
-
-
1
17
32
3
3
8
0.6
-
-
-
-
TYP
-
MAX
-
4.0
100
100
1
0.025
0.25
18
1.130
0.180
30
100
ns
-
-
-
-
-
-
-
-
-
-
-
-
200
100
4
70
128
12
14
nc
32
1.8
400
11
250
V
ns
o
C/W
UNITS
V
V
nA
nA
µA
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage Forward
Gate-Body Leakage Reverse
Zero Gate Voltage Drain Current
Rated Avalanche Current
Drain to Source On-State Volts
Drain to Source On Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Gate-Charge Threshold
Gate-Charge On State
Gate-Charge Total
Plateau Voltage
Gate-Charge Source
Gate-Charge Drain
Diode Forward Voltage
Reverse Recovery Time
Junction To Case
Junction To Ambient
-
-
-
-
-
A
V
Ω
nc
V
2
FRX130D, FRX130R, FRX130H
Typical Performance Curves
Unless Otherwise Specified
8
ID, DRAIN (A)
OPERATION IN THIS AREA
IS LIMITED BY r
DS(ON)
ID, DRAIN (A)
6
10
4
2
10ms
FRX130
0
100
50
CASE TEMPERATURE (T
C
)
FRX130
50
VDS DRAIN-TO-SOURCE (V)
100
FIGURE 1. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 2. SAFE OPERATING AREA CURVE CASE
TEMPERATURE = 25
o
C
80
NORMALIZED r
DS(ON)
4
RATED BVDSS
3
100V
2
50V
500V
200V
50
ID, DRAIN (A)
30
20
FRX130
100
500
TIME OF INDUCTIVE DISCHARGE (µs)
1E13
1E15
1E14
FLUENCE - NEUTRONS/cm
2
FIGURE 3. TYPICAL UNCLAMPED INDUCTIVE SWITCHING
FAILURE ONSET AVALANCHE MODE
FIGURE 4. NORMALIZED ON-RESISTANCE vs NEUTRON
FLUENCE N-CHANNEL
DRAIN CURRENT (A)
100
LIMITING INDUCTANCE (H)
1E-4
ILM = 10A
ILM = 30A
10
1E-5
ILM = 100A
ILM = 300A
1E-6
1
FRX130
1E8
1E9
GAMMA DOT - RAD (Si)/s
1E10
30
100
DRAIN SUPPLY (V)
GAMMA DOT
300
FIGURE 5. TYPICAL PHOTO CURRENT vs GAMMA RATE
FIGURE 6. DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA
DOT CURRENT TO I
LM
3
FRX130D, FRX130R, FRX130H
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
AS
IS REACHED
V
DS
L
+
CURRENT I
TRANSFORMER
AS
BV
DSS
t
P
I
AS
+
V
DD
V
DS
V
DD
-
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
≤
20V
50Ω
-
DUT
50V-150V
50Ω
t
AV
0V
t
P
FIGURE 7. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 8. UNCLAMPED ENERGY WAVEFORMS
V
DD
t
ON
t
D(ON)
t
OFF
t
D(OFF)
t
R
t
F
90%
R
L
V
DS
V
GS
= 12V
DUT
0V
R
GS
V
DS
90%
10%
10%
90%
V
GS
10%
50%
PULSE WIDTH
50%
FIGURE 9. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 10. RESISTIVE SWITCHING WAVEFORMS
4
FRX130D, FRX130R, FRX130H
18 Pin CLCC
18 PIN CERAMIC LEADLESS CHIP CARRIER
E
INCHES
SYMBOL
A
b
R
1
MILLIMETERS
MIN
2.34
0.51
6.99
4.45
1.78
8.64
6.10
2.42
MAX
2.84
0.76
7.49
5.46
2.03
9.14
7.11
2.66
NOTES
-
-
-
-
-
-
-
-
-
-
-
4
4
MIN
0.092
0.020
0.275
0.175
0.070
0.340
0.240
0.095
MAX
0.112
0.030
0.295
0.215
0.080
0.360
0.280
0.105
D
D
1
D
2
E
E
1
E
2
D
R
e
L
0.050 BSC
0.085
0.035
0.007
0.003
0.115
0.055
0.017
0.013
1.27 BSC
2.16
0.89
0.18
0.08
2.92
1.39
0.43
0.33
A
L
1
R
R
1
SEATING
PLANE
NOTES:
1. No current JEDEC outline for this package.
2. All exposed metallized areas shall be plated with a minimum of 50
microinches of gold over nickel unless otherwise stated.
3. Metallized castellations shall be connected to the seating plane
and extend upward toward top of package.
4. Corner shape (notch, radius, square, etc.) may vary at the manu-
facturer's option.
5. Unless otherwise specified, a minimum clearance of 0.010 inches
(0.25mm) shall be maintained between all metallized areas.
6. Controlling dimension: Inch.
7. Revision 1 dated 6-93.
E
1
E
2
D
2
D
1
1
2
L
1
e
b
L
ELEMENT
GATE
DRAIN
SOURCE
PAD
A
B
C
5
PINS CONNECTED
1, 2, 3, 4, 16, 17, 18
6, 7, 8, 9, 10, 11, 12, 13, 14, 15
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
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