IA6805E2
Microprocessor Unit
FEATURES
Preliminary Data Sheet
•
Form, Fit, and Function Compatible with the Harris
©
CDP6805E2CE and Motorola
©
MC146805E2
•
Internal 8-bit Timer with 7-Bit Programmable
Prescaler
•
On-chip Clock
•
Memory Mapped I/O
•
Versatile Interrupt Handling
•
True Bit Manipulation
•
Bit Test and Branch Instruction
•
Vectored Interrupts
•
Power-saving STOP and WAIT Modes
•
Fully Static Operation
•
112 Bytes of RAM
The IA6805E2 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces
replacement ICs using its MILES
TM
, or Managed IC Lifetime Extension System, cloning technology. This
technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible
with the original IC. MILES
TM
captures the design of a clone so it can be produced even as silicon
technology advances. MILES
TM
also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA6805E2 including functional and I/O descriptions, electrical characteristics, and applicable
timing.
Functional Block Diagram
RESET_N
OSC1
VDD
IRQ_N
LI
DS
RW_N
AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
A12
A11
A10
A9
A8
VSS
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
40 Pin DIP
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
OSC2
(6)
(5)
(4)
(3)
(2)
(1)
(44)
(43)
(42)
(41)
(40)
TIMER
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
B0
B1
B2
B3
B4
B5
A12
A11
A10
VSS
A9
A8
B7
B6
B5
B4
B6
B7
NC
AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
NC
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
LI
(2)
(39)
OSC1
PB0
NC
DS
IA6805E2
OSC2
RESET_N
(1)
(40)
VDD
TIMER
IRQ_N
RW_N
(39)
(38)
PB1
PB2
PB3
PB4
PB5
PB6
PB7
B0
B1
B2
B3
IA6805E2
44 Pin LCC
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
Copyright
©
2000
innovASIC
The End of Obsolescence™
www.innovasic.com
Customer Support:
Page 1 of 32
1-888-824-4184
IA6805E2
Microprocessor Unit
Functional Overview
I/O Signal Description
Preliminary Data Sheet
The table below describes the I/O characteristics for each signal on the IC. The signal names correspond to
the signal names on the pinout diagrams provided.
SIG N A L
NAME
I/O
N/A
I
I
DESCRIPTION
S o u r c e :
T h e s e t w o p i n s p r o v i d e p o w e r to t h e c h i p . V
D D
p r o v i d e s + 5 v o l t s ( ± 0 . 5 ) p o w e r
a n d V
SS
i s g r o u n d .
T T L :
I n p u t p i n t h a t c a n b e u s e d to r e s e t t h e M P U 's i n t e r n a l s t a t e b y p u l l i n g t h e r e s e t _ n
pin low.
T T L :
I n p u t p i n t h a t is l e v e l a n d e d g e s e n s i t i v e . C a n b e u s e d to r e q u e s t a n i n t e r r u p t
sequence.
T T L w ith s l e w r a t e c o n t r o l :
O u t p u t p i n u s e d to i n d i c a t e t h a t a n e x t o p c o d e f e t c h is in
p r o g r e s s . U s e d o n l y f o r c e r t a i n d e b u g g i n g a n d t e s t s y s t e m s . N o t c o n n e c t e d in n o r m a l
o p e r a t i o n . O v e r l a p s D ata S t r o b e ( D S ) s i g n a l . T h i s o u t p u t is c a p a b l e o f d r i v i n g o n e
standard TTL load and 50pF.
T T L w ith s l e w r a t e c o n t r o l :
O u t p u t p i n u s e d to t r a n s f e r d a t a to o r f r o m a p e r i p h e r a l o r
m e m o r y . D S o c c u r s a n y t i m e t h e M P U d o e s a d a t a r e a d o r w rite a n d d u r i n g d a t a t r a n s f e r
to o r f r o m i n t e r n a l m e m o r y . D S is a v a i l a b l e a t f
O S C
÷
5 w h e n t h e M P U is n o t in t h e W A I T
or STOP mode. This output is capable of driving one standard TTL load and 130pF.
T T L w ith s l e w r a t e c o n t r o l :
O u t p u t p i n u s e d to i n d i c a t e t h e d i r e c t i o n o f d a t a t r a n s f e r
from internal m e m o r y , I / O registers, and external peripheral devices and m e m o r i e s .
I n d i c a t e s to a s e l e c t e d p e r i p h e r a l w h e t h e r t h e M P U is to r e a d ( R W _ n h i g h ) o r w r i t e
( R W _ n l o w ) d a t a o n t h e n e x t d a t a s t r o b e . T h i s o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d
TTL load and 130pF.
T T L w ith s l e w r a t e c o n t r o l :
O u t p u t s t r o b e u s e d to i n d i c a t e t h e p r e s e n c e o f an a d d r e s s
o n t h e 8 - b i t m u l t i p l e x e d b u s . T h e A S l i n e is u s e d to d e m u l t i p l e x t h e e i g h t l e a s t s i g n i f i c a n t
a d d r e s s b i t s f r o m t h e d a t a b u s . A S is a v a i l a b l e a t f
O S C
÷
5 w h e n t h e M P U is n o t in t h e
W A I T o r S T O P m o d e s . T h i s o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d T T L l o a d a n d
130pF.
T T L w ith s l e w r a t e c o n t r o l :
T h e s e 16 l i n e s c o n s t i t u t e I n p u t / O u t p u t p o r t s A a n d B .
E a c h l i n e is i n d i v i d u a l l y p r o g r a m m e d to b e e i t h e r an i n p u t o r o u t p u t u n d e r s o f t w a r e
c o n t r o l o f t h e D ata D i r e c t i o n R e g i s t e r ( D D R ) a s s h o w n b e l o w in
T a b l e 1
a n d
F i g u r e 2
.
T h e p o r t I / O is p r o g r a m m e d b y w r i t i n g t h e c o r r e s p o n d i n g b i t in t h e D D R to a " 1 " f o r
o u t p u t a n d a " 0 " f o r i n p u t . In t h e o u t p u t m o d e t h e b i t s are l a t c h e d a n d a p p e a r on t h e
c o r r e s p o n d i n g o u t p u t p i n s . A ll t h e D D R 's a r e i n i t i a l i z e d to a " 0 " o n r e s e t . T h e o u t p u t
p o r t r e g i s t e r s a r e n o t i n i t i a l i z e d o n r e s e t . E a c h o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d
TTL load and 50pF.
T T L w ith s l e w r a t e c o n t r o l :
T h e s e f i v e o u t p u t s c o n s t i t u t e t h e h i g h e r o r d e r n o n -
m u l t i p l e x e d a d d r e s s l i n e s . E a c h o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d T T L l o a d a n d
130pF.
T T L w ith s l e w r a t e c o n t r o l :
T h e s e b i - d i r e c t i o n a l l i n e s c o n s t i t u t e t h e l o w e r o r d e r
a d d r e s s e s a n d d a t a . T h e s e l i n e s a r e m u l t i p l e x e d w ith a d d r e s s p r e s e n t at a d d r e s s s t r o b e
t i m e a n d d a t a p r e s e n t a t d a t a s t r o b e t i m e . W h e n in t h e d a t a m o d e , t h e s e l i n e s a r e b i -
d i r e c t i o n a l , t r a n s f e r r i n g d a t a to a n d f r o m m e m o r y a n d p e r i p h e r a l d e v i c e s a s i n d i c a t e d b y
t h e R W _ n p i n . A s o u t p u t s , t h e s e lines are c a p a b l e o f d r i v i n g o n e s t a n d a r d T T L l o a d a n d
130pF.
T T L :
Input used to control the internal tim er/counter circuitry.
T T L O scillator input/output:
These pins provide control input for the on-chip clock
o s c i l l a t o r c i r c u i t s . E i t h e r a c r y s t a l o r e x t e r n a l c l o c k is c o n n e c t e d to t h e s e p i n s to p r o v i d e
a s y s t e m c l o c k . T h e c r y s t a l c o n n e c t i o n is s h o w n in
F i g u r e 3
. T h e O S C 1 to b u s
transitions for system designs using oscillators slower than 5M H z is shown in
Figure 4
.
T h e c i r c u i t s h o w n in
F i g u r e 3
is r e c o m m e n d e d w h e n u s i n g a c r y s t a l . A n e x t e r n a l C M O S
o s c i l l a t o r is r e c o m m e n d e d w h e n u s i n g c r y s t a l s o u t s i d e t h e s p e c i f i e d r a n g e s . T o m i n i m ize
o u t p u t distortion a n d start-up stabilization tim e , t h e crystal a n d c o m p o n e n t s s h o u l d b e
mounted as close to the input pins as possible.
W h e n an e x t e r n a l c l o c k is u s e d , it s h o u l d b e a p p l i e d to t h e O S C 1 i n p u t w ith t h e O S C 2
input not connected, as shown in
Figure 3
.
V
D D
a n d V
SS
(Power and Ground)
RESET_n
(R e s e t )
IR Q _ n
(Interrupt Request)
LI
(L o a d I n s t r u c t i o n )
O
DS
(D a t a S t r o b e )
O
RW_n
(R e a d / W rite)
O
AS
(A d d r e s s S t r o b e )
O
PA0-PA7/PB0-PB7
(Input/Output Lines)
I/O
A8-A12
(H i g h O r d e r A d d r e s s L i n e s )
O
B0-B7
(A d d r e s s / D a t a B u s )
I/O
T im e r
OSC1, OSC2
(System C lock)
I
I/O
C rystal
External Clock
Copyright
©
2000
innovASIC
The End of Obsolescence™
www.innovasic.com
Customer Support:
Page 3 of 32
1-888-824-4184
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