Page 1 of 32
IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
FEATURES
•
Form, Fit, and Function Compatible
with the Intel
®
80C152
•
Packaging options available
−
48 Pin Plastic or Ceramic DIP
−
68 Pin Plastic or Ceramic LCC
•
8051 Core with:
−
Direct Memory Access(DMA)
−
Global Serial Channel (GSC)
−
MCS
®
- 51 Compatible UART
−
Two Timers/Counters
−
Maskable Interrupts
•
Memory
−
256 Bytes Internal RAM
−
64K Bytes Program Memory
−
64K Bytes Data Memory
•
5 or 7 I/O Ports
•
Up to 16.5 MHz Clock Frequency
•
Two-Channel DMA With Multiple
Transfer Modes
•
GSC Provides Support for Multiple
Protocols
−
CSMA/CD
−
SDLC/HDLC
−
User Definable
•
Separate Transmit & Receive FIFOs
•
Special Protocol Features
−
Up to 2.0625 Mbps Serial
Operation
−
CSMA and SDLC Frame Formats
with CRC Checking
−
Manchester, NRZ, & NRZI Data
Encoding
−
Collision Detection & Resolution
in CSMA Mode
−
Selectable Full/Half Duplex
(GRXD) P1.0
(GTXD) P1.1
(DENn) P1.2
(TXCn) P1.3
(RXCn) P1.4
(HLDn) P1.5
(HLDAn) P1.6
P1.7
RESETn
(RXD) P3.0
(TXD) P3.1
(INT0n) P3.2
(INT1n) P3.3
(T0) P3.4
(T1) P3.5
(WRn) P3.6
(RDn) P3.7
(A / D0) P0.0
(A / D1) P0.1
(A / D2) P0.2
(A / D3) P0.3
XTAL2
XTAL1
Vss
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
IA80152
(48)
(47)
VDD
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
EA
ALE
PSENn
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
P0.7 (A / D7)
P0.6 (A / D6)
P0.5 (A / D5)
P0.4 (A / D4)
48 Pin DIP
(46)
JA/JC
(45)
(44)
(43)
(42)
(41)
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
Figure 1 - 48 Pin DIP Pinout
Copyright
©
2000
innovASIC
[_________The
End of Obsolescence™
Page 2 of 32
IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
P1.0 (GRXD)
P1.1 (GTXD)
P1.2 (DENn)
P1.4 (RXCn)
P1.5 (HLDn)
P1.3 (TXCn)
VDD
P4.0
P4.1
P4.2
P4.3
(62)
(9)
(8)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(68)
(67)
(66)
(65)
(64)
(63)
(HLDAn) P1.6
P1.7
N.C.
RESETn
(RXD) P3.0
(TXD) P3.1
(INT0n) P3.2
N.C.
(INT1n) P3.3
(T0) P3.4
N.C.
N.C.
N.C.
(T1) P3.5
(WRn) P3.6
(RDn) P3.7
N.C.
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(61)
(60)
(59)
P4.4
N.C.
N.C.
N.C.
N.C.
Vss
P4.5
P4.6
P4.7
N.C.
EA
ALE
PSENn
N.C.
N.C.
N.C.
N.C.
N.C.
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
IA82510
68 Pin LCC
JA/JC
(58)
(57)
(56)
(55)
(54)
(53)
(52)
(51)
(50)
(49)
(48)
(47)
(46)
(45)
(44)
Vss
N.C.
N.C.
N.C.
(A8) P2.0
(A / D0) P0.0
(A / D1) P0.1
(A / D2) P0.2
(A / D3) P0.3
(A / D4) P0.4
(A / D5) P0.5
(A / D6) P0.6
(A / D7) P0.7
(A9) P2.1
P4.3
(62)
XTAL2
XTAL1
Figure 2 - 68 Lead LCC Pinout - JA/JC Versions
P1.0 (GRXD)
P1.1 (GTXD)
P1.2 (DENn)
P1.4 (RXCn)
P1.5 (HLDn)
P1.3 (TXCn)
VDD
P6.6
P6.5
P6.0
P6.1
P4.0
P4.1
P4.2
(68)
(67)
(66)
(65)
(64)
(63)
(HLDAn) P1.6
P1.7
EBEN
RESETn
(RXD) P3.0
(TXD) P3.1
(INT0n) P3.2
P5.0
(INT1n) P3.3
(T0) P3.4
P5.1
P5.2
P5.3
(T1) P3.5
(WRn) P3.6
(RDn) P3.7
N.C.
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(61)
(60)
(59)
(9)
(8)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
P4.4
Vss
(A10) P2.2
P4.5
P4.6
P4.7
P6.3
EA
ALE
PSENn
EPSENn
P6.2
P6.7
P6.4
P5.7
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
IA82510
68 Pin LCC
JB/JD
(58)
(57)
(56)
(55)
(54)
(53)
(52)
(51)
(50)
(49)
(48)
(47)
(46)
(45)
(44)
P5.4
P5.5
P5.6
Vss
(A8) P2.0
(A / D0) P0.0
(A / D1) P0.1
(A / D2) P0.2
(A / D3) P0.3
(A / D4) P0.4
(A / D5) P0.5
(A / D6) P0.6
(A / D7) P0.7
(A9) P2.1
XTAL2
XTAL1
Figure 3 - 68 Lead LCC Pinout - JB/JD Versions
Copyright
©
2000
innovASIC
[_________The
End of Obsolescence™
(A10) P2.2
Page 3 of 32
IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
The IA80C152 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces
replacement ICs using its MILES
TM
, or Managed IC Lifetime Extension System, cloning technology.
This technology produces replacement ICs far more complex than "emulation" while ensuring they
are compatible with the original IC. MILES
TM
captures the design of a clone so it can be produced
even as silicon technology advances. MILES
TM
also verifies the clone against the original IC so that
even the "undocumented features" are duplicated. This data sheet documents all necessary
engineering information about the IA80C152 including functional and I/O descriptions, electrical
characteristics, and applicable timing.
INTEL is a registered trademark of Intel Corporation
DESCRIPTION
The IA80C152 is a Universal Communications Controller (UCC) that is pin-for-pin compatible
with the Intel™ 80C152. This version of the UCC is a ROMless version. The ROM version is
identified as the 83C152 and can be easily derived from the 80C152 using a customer furnished
ROM program. The IA80C152 can be programmed with the same software development tools and
can transmit and receive using the same communication protocols as the Intel™ 80C152 making the
IA80C152 a drop-in replacement. Table 1 below cross-references IA80C152 versions with
protocol, package, and I/O Port capability. Pinout diagrams are provided in figures 1, 2, and 3.
Table 1 - IC Version Differences
CSMA/CD,
SDLC/HDLC,
5 I/O 7 I/O
User-Defined
Ports Ports
48 Pin DIP
√
√
√
√
√
√
√
√
√
√
innovASIC
Part Number
IA80C152JA
IA80C152JB
IA80C152JC
IA80C152JD
68 Lead LCC
√
√
√
√
The only difference between The innovASIC 80C152 and the Intel™ 80C152 is that all protocols
are available in all IC versions. Originally, the Intel™ 80C152 JC and JD versions were limited to
SDLC/HDLC only. Also, innovASIC will support a ROM version (83152) in any of the JA, JB, JC,
or JD versions.
The IA80C152 is partitioned into three major functional units identified as the C8051, the Direct
Memory Access (DMA) Controller, and the Global Serial Channel (GSC). The C8051 is
implemented using a CAST, Inc. Intellectual Property (IP) core. This core is instruction set
compatible with the 80C51BH, and contains compatible peripherals including a UART interface
and timers. The special function registers (SFRs) and interrupts are modified from the original
8051BH to accommodate the additional DMA controller and GSC peripherals.
The DMA Controller is a 2 channel, 8-bit device that is 16-bit addressable. Either channel can
access any combination of reads and writes to external memory, internal memory, or the SFR's.
Various modes allow the DMA to access the UART, GSC, SFRs, and internal and external memory
as well as provide for external control. Since there is only 1 data/program memory bus, only one
DMA channel or the microcontroller can have control at any give time. Arbitration within the
device makes this control transparent to the programmer.
Copyright
©
2000
innovASIC
[_________The
End of Obsolescence™
Page 4 of 32
IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
The GSC is a serial interface that can be programmed to support CSMA/CD, SDLC, user definable
protocols, and limited HDLC. Protocol specific features are supported in hardware such as address
recognition, collision resolution, CRC generation and errors, automatic re-transmission, and
hardware acknowledge. The CSMA/CD protocol meets the requirements of ISO/IEC 8802-3 and
ANSI/IEEE Std 802.3 to the extent implemented in the original IC. The SDLC protocol meets
the requirements of IBM GA27-3093-04 to the extent implemented in the original IC.
Functional Block Diagram
Figure 4 shows the major functional blocks of the IA80C152. Each version of the IA80C152
function identically to each other with the exception of the 2 additional I/O ports (Port 5 and
Port 6) in the JB and JD versions.
I/O for Memory, GSC, DMA, UART, Interrupts, Timers
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Memory
Control
XTAL
Reset
Clock Gen.
& Timing
256x8 RAM
C8051
CPU
Control
Address/Data
UART
Interrupts
Timers
DMA
GSC
= JB and JD Versions Only
Figure 4 - Functional Block Diagram
Copyright
©
2000
innovASIC
[_________The
End of Obsolescence™
Page 5 of 32
IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
I/O Signal Description
Table 2 below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided above. (!) Denotes active Low.
Table 2 - I/O Signal Descriptions
Signal Name
!EA
!EPSEN
!PSEN
!RESET
Description
External Access enable. Since there is no internal ROM in the
80C152, this signal has no function in the JA and JC versions. For
the JB and JD versions, controls program memory fetch locations.
E-bus Program Store ENable. When EBEN is 1, this signal is the
read strobe for external program memory.
Program Store ENable. When EBEN is 0, this signal is the read
strobe for external program memory.
Reset. When this signal is low for 3 machine cycles, the device is put
into reset. The GSC may continue transmitting after reset is applied.
An internal pull-up allow the use of an external capacitor to generate
a power-on reset.
Address Latch Enable. Latches the low-byte of external memory.
E-Bus ENable. In conjunction with EA, EBEN designates program
memory fetches from either Port 0,2 or Port 5,6.
Port 0 - open drain 8-bit bi-directional port that bit addressable and
can drive up to 8 LS TTL inputs. The port signals can be used as
high impedance inputs.
This port also provides the low-byte of the multiplexed address and
data bus depending on the state of !EBEN.
ALE
EBEN
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0 - GRXD, GSC Receive
P1.1 - GTXD, GSC Transmit
P1.2 - !DEN, Driver Enable
P1.3 - !TXC, External Transmit Clock
P1.4 - !RXC, External Receive Clock
P1.5 - !HLD, DMA Hold
P1.6 - !HLDA, DMA Hold Acknowledge
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0 - RXD, UART Receive
P3.1 - TXD, UART Transmit
P3.2 - !INT0, External Interrupt 0
P3.3 - !INT1, External Interrupt 1
P3.4 - T0, Timer 0 External Input
P3.5 - T1, Timer 1 External Input
P3.6 - !WR, External Data Memory Write Strobe
P3.7 - !RD, External Data Memory Read Strobe
P4.0
P4.1
P4.2
Port 1 - 8-bit bi-directional port that is bit addressable. To use a port
signal as an input, write a 1 to the port location. Internal pull-ups pull
the input high and source current when the input is driven low. To
use a port signal as an output, a 1 or 0 written to the port location is
presented at the output.
Port signals in this port also serve as I/O for 80C152 functions.
These I/O signals are defined next to the port name.
Port 2 - 8-bit bi-directional port that is bit addressable. To use a port
signal as an input, write a 1 to the port location. Internal pull-ups pull
the input high and source current when the input is driven low. To
use a port signal as an output, a 1 or 0 written to the port location is
presented at the output.
This port also provides the high-byte of the multiplexed address and
data bus depending on the state of !EBEN.
Port 3 - 8-bit bi-directional port that is bit addressable. To use a port
signal as an input, write a 1 to the port location. Internal pull-ups pull
the input high and source current when the input is driven low. To
use a port signal as an output, a 1 or 0 written to the port location is
presented at the output.
Port signals in this port also serve as I/O for 80C152 functions.
These I/O signals are defined next to the port name.
Port 4 - 8-bit bi-directional port that is bit addressable. To use a port
signal as an input, write a 1 to the port location. Internal pull-ups pull
the input high and source current when the input is driven low. To
Copyright
©
2000
innovASIC
[_________The
End of Obsolescence™
DSP 与 ARM 处理器
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