SMM151/152
Single-channel Voltage/Current Monitors and Voltage Marginers
FEATURES & APPLICATIONS
•
Capable of margining supplies with trim inputs using
either positive or negative trim pin control
•
Wide Margin range of 0.3V to VDD with internal
reference
•
Differential Voltage Sensing of the DC-DC converter
output voltage
•
Supply-side current monitoring (10-bit ADC)
2
•
10-bit ADC readout of supply voltage over I C bus
•
Margining Controlled Via:
2
I C Command
Input Pins (M
UP
, M
DN
)
•
Two programmable general purpose sensor inputs
(COMP1/2) – UV/OV with FAULT Output
•
Programmable glitch filters (COMP1/2)
•
Programmable internal COMP1/2 VREF: 0.5V or 1.25V
•
Operates from 2.7V to 5.5V supply
•
Current sensing from 4.0V to 15V supply
•
Programmable, general purpose I/Os (SMM152)
•
General Purpose 256-Byte EEPROM with Write Protect
2
•
I C 2-wire serial bus for programming configuration and
monitoring status
•
28-lead 5x5 QFN
Preliminary Datasheet
INTRODUCTION
The SMM151/152 are highly accurate power supply
voltage/current supervisors and monitors with provisions for
voltage margining of the monitored supply. The parts include
an internal voltage reference to accurately monitor and margin
the supply to within ±1%. The SMM151/152 have the capability
to margin over a wide range from 0.3V to VDD using the
internal reference and can read the differential voltage of the
supply and voltage drop of the current sense resistor over the
I
2
C bus using an on-chip 10-bit ADC. The margin levels are set
using the I
2
C serial bus. The devices initiate margining via the
2
I C bus or by using the M
UP
or M
DN
inputs. Once the pre-
programmed margin target voltage is reached, the
SMM151/152 hold the converter at this voltage until receiving
an I
2
C command or de-asserting the margin input pin. When
the SMM151/152 are not margining, the TRIM output pin is
held in a high impedance state allowing the converter to
operate at its nominal set point.
Two general purpose input pins are provided for sensing under
or over-voltage conditions. A programmable glitch filter
associated with these inputs allows the user to ignore spurious
noise signals. A FAULT# pin is asserted once either input set
point is exceeded. The SMM152 also provides four
programmable general-purpose inputs/outputs.
Using the I
2
C interface, a host system can communicate with
the SMM151/152 status register and utilize 256-bytes of
nonvolatile memory.
•
•
•
Applications
In-system test and control of Point-of-Load (POL)
Power Supplies for Multi-voltage Processors, DSPs
and ASICs
Routers, Servers, Storage Area Networks
TYPICAL APPLICATION
4.0V-15V
2.7V-5.5V
R
S
CAPC
CS-
CS+
VDD
GND
VDD_CAP
COMP1
V1
Margin
Commands
Status
Outputs
I
2
C
Interface
MUP
MDN
FAULT#
READY
SDA
SCL
A0-A2
WP
(GPIO0)
(GPIO1)
(GPIO2)
(GPIO3)
COMP2
VREF
VIN
SMM151
(SMM152)
VOUT+
SEN+
TRIM
TRIM
CAPM+
VOUT-
SEN-
DC-DC Converter
CAPM-
VM+
VM-
Figure 1 – Application with the SMM151/152 used to Monitor and Margin a DC/DC Converter.
Note: This is an applications example only. Some components and values are not shown.
© SUMMIT
Microelectronics, Inc. 2007 • 757 N. Mary Avenue • Sunnyvale CA 94085 • Phone 408 523-1000 • FAX 408 523-1266
http://www.summitmicro.com/
2131 2.1 8/15/2008
1
SMM151/152
Preliminary Datasheet
GENERAL DESCRIPTION
The SMM151 and SMM152 are capable of margining the
DC output voltage of LDOs or DC/DC converters that
use a trim/adjust pin. The Margin function is
programmable over a standard 2-wire I
2
C serial data
interface and is used to set the margin low/high DC
output voltages. The devices are also capable of
monitoring the differential output voltage and the input
current of DC/DC converters, thereby providing real-time
power information to the system.
In margining mode the user communicates with the
SMM151/152 via the I
2
C serial data bus to select the
desired values for margining. This allows the part to
margin the supplies up or down to these set values
either through asserting the MUP and MDN pins or by
writing to the margin register directly. The margin high
and margin low voltage settings can range from 0.3V to
VDD around the converter’s nominal output voltage
setting depending on the specified margin range of the
DC-DC converter and/or system components, usually
±10%.
When the SMM151/152 receive the command to margin,
the TRIM output will begin adjusting the supply to the
selected margin voltage. This is accomplished by
incrementing (or decrementing) an internal counter
based on the digital comparison between the voltage
margin target value and that read by the ADC from the
VM+ - VM- differential input. This operation is repeated
until the 2 values are equal, after which the
SMM151/152 hold the TRIM output pin at the voltage
required to maintain the margin setting. An I
2
C command
or de-assertion of the MUP/MDN pin will return the TRIM
output pin to a high impedance state thus allowing the
converter to return to its nominal operating voltage.
The SMM151 and SMM152 sense converter input
current using a sense resistor connected in series with
the converter supply whose terminals are connected to
the CS+ and CS- pins. The internal ADC, also used for
measuring the converter’s output voltage, is used to
measure the converter’s input current using the voltage
dropped across the current sense resistor R
S
(see
Figure 1).
The SMM151/152 have two additional input pins and
one additional output pin. The input pins, COMP1 and
COMP2, are high impedance inputs, each connected to
a comparator and compared against the internal
reference (VREF: 0.5V or 1.25V). Each comparator can
be independently programmed to monitor for UV or OV.
When either of the COMP1 or COMP2 inputs are in fault
the open-drain FAULT# output will be pulled low. A
configuration option exists to disable the FAULT# output
during margining.
The SMM152 also provides four programmable general-
purpose inputs/outputs. The power-on state of these
I/Os is determined via non-volatile (NV) memory. Volatile
programming allows the user to select the logic level
(HIGH or LOW) of each I/O, which can also be read via
a status register.
Programming of the SMM151/152 is performed over the
industry standard I
2
C 2-wire serial data interface. A
status register is available to read the state of the part
and a Write Protect (WP) pin is available to prevent
writing to the configuration registers and EE memory.
Summit Microelectronics, Inc
2131 2.1 8/15/2008
2
SMM151/152
Preliminary Datasheet
INTERNAL BLOCK DIAGRAM
VREF
READY
FAULT#
VDD
VDD_CAP
GND
COMP1
VREF
VREF = 1.25V
OV/UV
0.5V/1.25V
Output
Control
Glitch
Filter
OV/UV
COMP2
50kΩ
Up/Dn
MUP
MDN
Margin
Target
Digital
Comparator
Halt
Control
Logic
8-bit DAC
SW1
TRIM
50kΩ
Clock
A0
A1
A2
SCL
SDA
WP
GPIO0
GPIO1
GPIO2
GPIO3
I
2
C
Interface
10Bit
ADC
SW2
MUX
CAPM+
CAPM-
Control
Logic
SMM152
EE
Configuration
Registers
& Memory
250kΩ
25kΩ
25kΩ
VM+
VM-
CAPC
CS+
DIFF
AMP
CS-
Figure 2 – SMM151 and SMM152 Controller Internal Block Diagram.
PACKAGE AND PIN DESCRIPTION
SDA
(GPIO3)
VREF
MDN
MUP
VDD_CAP
(GPIO2)
28 27 26 25 24 23 22
1
2
3
4
5
6
7
8
9 10 11 12 13 14
21
20
19
18
17
16
15
28-Pad 5x5 QFN
Top View
() applies on SMM152
Pin 1
SCL
A2
(GPIO0)
A1
READY
A0
GND
SMM150
GND
VDD
TRIM
COMP1
CS+
CS-
CAPC
VM-
Summit Microelectronics, Inc
WP
(GPIO1)
CAPM+
FAULT#
COMP2
CAPM-
VM+
2131 2.1 8/15/2008
3
SMM151/152
Preliminary Datasheet
PIN DESCRIPTIONS
Pin
Number
28
1
2
4
6
3, 9, 22, 27
8
10, 13
20
14
15
18
17
26
16
21
23
7
24
25
19
12
11
Pin
Type
I/O
I
I
I
I
I/O
NC
I
CAP
O
I
I
I
I
PWR
O
PWR
PWR
GND
I
I
I
I
O
Pin Name
SDA
SCL
A2
A1
A0
GPIO0,1,2,3
NC
WP
CAPM+, -
TRIM
VM+
VM-
CS+
CS-
VREF
CAPC
VDD
VDD_CAP
GND
MUP
MDN
COMP1
COMP2
FAULT#
Pin Description
I
2
C Bi-directional data line
I
2
C clock input.
The address pins are biased either to VDD, GND or left floating. This allows
for a total of 21 distinct device addresses. When communicating with the
SMM151/2 over the 2-wire bus these pins provide a mechanism for
assigning a unique bus address.
SMM152: General purpose inputs/outputs.
SMM151: No Connect.
Programmable Write Protect active high/low input. When asserted, writes to
the configuration registers and general purpose EE are not allowed. The
WP input is internally tied to VDD with a 50KΩ resistor.
External capacitor inputs used to filter the VM+/VM- inputs, 0.22µF.
Output voltage used to control and/or margin converter voltages. Connect to
the converter trim input.
Voltage monitor input. Connect to the DC-DC converter positive sense line
or it’s +Vout pin.
Voltage monitor input. Connect to the DC-DC converter negative sense line
or it’s -Vout pin.
Current monitor input + side. Connect to the input supply side of the current
sense resistor.
Current monitor input - side. Connect to the load side of the current sense
resistor.
Internal reference voltage of 1.25V. Connect to GND through a 0.1uF
capacitor to improve noise immunity.
External capacitor input used to filter the CS+/CS- input. Typical value: 1uF.
Power supply of the part.
External capacitor input used to filter the internal VDD supply rail.
Ground of the part. The SMM151/2 ground pin should be connected to the
ground of the device under control or to a star point ground. PCB layout
should take into consideration ground drops.
Margin up command input. Asserted high. The MUP input is internally tied to
VDD with a 50KΩ resistor.
Margin down command input. Asserted high. The MDN input is internally
tied to VDD with a 50KΩ resistor.
COMP1 and COMP2 are high impedance inputs, each connected internally
to a comparator and compared against the internally programmable VREF
voltage. Each comparator can be independently programmed to monitor for
UV or OV. The monitor level is set externally with a resistive voltage
divider.
When either of the COMP1 or COMP2 inputs are in fault the open-drain
FAULT# output will be pulled low. A configuration option exists to disable
the FAULT# output while the device is margining.
Summit Microelectronics, Inc
2131 2.1 8/15/2008
4
SMM151/152
Preliminary Datasheet
PIN DESCRIPTIONS (CONTINUED)
5
29
I/O
GND
READY
GND
Programmable active high/low open drain output indicates that VM+ - VM-
is at its set point. When programmed as an active high output, READY can
also be used as an input. When pulled low, it will latch the state of the
comparator inputs.
GND. The bottom side metal plate (Pad 29) should be connected on the
PCB for optimized noise performance.
Summit Microelectronics, Inc
2131 2.1 8/15/2008
5
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