CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Guaranteed by design; not production tested
Electrical Specifications
PARAMETER
V
CC
SUPPLY CURRENT
Input Bias Supply Current
POWER-ON RESET
Rising V
CC
POR Threshold
V
CC
POR Threshold Hysteresis
OSCILLATOR
Switching Frequency
Test Conditions: V
CC
= 12V, T
J
= 0 to 85°C, Unless Otherwise Noted.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
VCC
V
POR
V
CC
= 12V; disabled
4
5.2
7
mA
3.9
0.30
4.1
0.35
4.3
0.40
V
V
f
OSC
f
OSC
ISL8105C
ISL8105I
ISL8105AC
ISL8105AI
270
240
540
510
300
300
600
600
1.5
330
330
660
660
kHz
kHz
kHz
kHz
V
P-P
Ramp Amplitude (Note 2)
REFERENCE
Reference Voltage Tolerance
ΔV
OSC
ISL8105C
ISL8105I
-1.0
-1.5
-
-
0.600
+1.0
+1.5
%
%
V
Nominal Reference Voltage
ERROR AMPLIFIER
DC Gain (Note 2)
Gain-Bandwidth Product (Note 2)
Slew Rate (Note 2)
GATE DRIVERS
Upper Gate Source Impedance
Upper Gate Sink Impedance
Lower Gate Source Impedance
Lower Gate Sink Impedance
Upper Gate Source Impedance
V
REF
GAIN
GBWP
SR
-
-
-
96
20
9
-
-
-
dB
MHz
V/μs
Ω
Ω
Ω
Ω
Ω
R
UG-SRCh
R
UG-SNKh
R
LG-SRCh
R
LG-SNKh
R
UG-SRCl
V
CC
= 14.5V; I = 50mA
V
CC
= 14.5V; I = 50mA
V
CC
= 14.5V; I = 50mA
V
CC
= 14.5V; I = 50mA
V
CC
= 4.25V; I = 50mA
-
-
-
-
-
3.0
2.7
2.4
2.0
3.5
-
-
-
-
-
3
FN6306.0
June 6, 2006
ISL8105, ISL8105A
Electrical Specifications
PARAMETER
Upper Gate Sink Impedance
Lower Gate Source Impedance
Lower Gate Sink Impedance
PROTECTION/DISABLE
OCSET Current Source
I
OCSET
V
DISABLE
ISL8105C; LGATE/OCSET = 0V
ISL8105I; LGATE/OCSET = 0V
Disable Threshold (COMP/SD pin)
19.5
18.0
0.375
21.5
21.5
0.400
23.5
23.5
0.425
μA
μA
V
Test Conditions: V
CC
= 12V, T
J
= 0 to 85°C, Unless Otherwise Noted.
(Continued)
SYMBOL
R
UG-SNKl
R
LG-SRCl
R
LG-SNKl
TEST CONDITIONS
V
CC
= 4.25V; I = 50mA
V
CC
= 4.25V; I = 50mA
V
CC
= 4.25V; I = 50mA
MIN
-
-
-
TYP
2.7
2.75
2.1
MAX
-
-
-
UNITS
Ω
Ω
Ω
Functional Pin Description
V
CC
(Pin 5)
This pin provides the bias supply for the ISL8105, as well as
the lower MOSFET’s gate, and the BOOT voltage for the
upper MOSFET’s gate. An internal 5V regulator will supply
bias if V
CC
rises above 6.5V (but the LGATE/OCSET and
BOOT will still be sourced by V
CC
). Connect a well-
decoupled 5V or 12V supply to this pin.
Use COMP/SD, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.
Pulling COMP/SD low (V
DISABLE
= 0.4V nominal) will
shut-down (disable) the controller, which causes the
oscillator to stop, the LGATE and UGATE outputs to be held
low, and the soft-start circuitry to re-arm. The external pull-
down device will initially need to overcome up to 5mA of
COMP/SD output current. However, once the IC is disabled,
the COMP output will also be disabled, so only a 20µA
current source will continue to draw current.
When the pull-down device is released, the COMP/SD pin
will start to rise, at a rate determined by the 20µA charging
up the capacitance on the COMP/SD pin. When the
COMP/SD pin rises above the V
DISABLE
trip point, the
ISL8105 will begin a new Initialization and soft-start cycle.
FB (Pin 6)
This pin is the inverting input of the internal error amplifier.
Use FB, in combination with the COMP/SD pin, to
compensate the voltage-control feedback loop of the
converter. A resistor divider from the output to GND is used
to set the regulation voltage.
GND (Pin 3)
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
LGATE/OCSET (Pin 4)
Connect this pin to the gate of the lower MOSFET; it provides
the PWM-controlled gate drive (from V
CC
). This pin is also
monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
During a short period of time following Power-On Reset
(POR) or shut-down release, this pin is also used to
determine the overcurrent threshold of the converter.
Connect a resistor (R
OCSET
) from this pin to GND. See the
Overcurrent Protection
section for equations. An
overcurrent trip cycles the soft-start function, after two
dummy soft-start time-outs. Some of the text describing the
LGATE function may leave off the OCSET part of the name,
when it is not relevant to the discussion.
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET, and
the drain of the lower MOSFET. It is used as the sink for the
UGATE driver, and to monitor the voltage drop across the
lower MOSFET for overcurrent protection. This pin is also
monitored by the adaptive shoot-through protection circuitry
to determine when the upper MOSFET has turned off.
UGATE (Pin 2)
Connect this pin to the gate of upper MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
Functional Description
Initialization (POR and OCP sampling)
Figure 1 shows a simplified timing diagram. The Power-On-
Reset (POR) function continually monitors the bias voltage at
the V
CC
pin. Once the rising POR threshold is exceeded
(V
POR
~4V nominal), the POR function initiates the
Overcurrent Protection (OCP) sample and hold operation
(while COMP/SD is ~1V). When the sampling is complete,
V
OUT
begins the soft-start ramp.
BOOT (Pin 1)
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive an N-channel MOSFET (equal to
V
CC
minus the on-chip BOOT diode voltage drop), with
respect to PHASE.
COMP/SD (Pin 7)
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
4
FN6306.0
June 6, 2006
ISL8105, ISL8105A
If the COMP/SD pin is held low during power-up, that will just
delay the initialization until it is released, and the COMP/SD
voltage is above the V
DISABLE
trip point.
sets up a voltage that will represent the OCSET trip point. At
T2, there is a variable time period for the OCP sample and hold
operation (0 to 3.4ms nominal; the longer time occurs with the
higher overcurrent setting). The sample and hold uses a digital
counter and DAC to save the voltage, so the stored value does
not degrade, for as long as the V
CC
is above V
POR
. See the
Overcurrent Protection
section for more details on the
equations and variables. Upon the completion of sample and
hold at T3, the soft-start operation is initiated, and the output
voltage ramps up between T4 and T5.
V
CC
(2V/DIV)
~4V POR
V
OUT
(1V/DIV)
COMP/SD (1V/DIV)
Soft-Start and Pre-Biased Outputs
Functionally, the soft-start internally ramps the reference on the
non-inverting terminal of the error amp from zero to 0.6V in a
nominal 6.8ms The output voltage will thus follow the ramp,
from zero to final value, in the same 6.8ms (the actual ramp
seen on the V
OUT
will be less than the nominal time, due to
some initialization timing, between T3 and T4).
The ramp is created digitally, so there will be 64 small discrete
steps. There is no simple way to change this ramp rate
externally, and it is the same for either frequency version of the
IC (300kHz or 600kHz).
After an initialization period (T3 to T4), the error amplifier
(COMP/SD pin) is enabled, and begins to regulate the
converter’s output voltage during soft-start. The oscillator’s
triangular waveform is compared to the ramping error amplifier
voltage. This generates PHASE pulses of increasing width that
charge the output capacitors. When the internally generated
soft-start voltage exceeds the reference voltage (0.6V), the soft-
start is complete, and the output should be in regulation at the
expected voltage. This method provides a rapid and controlled
output voltage rise; there is no large inrush current charging the
output capacitors. The entire start-up sequence from POR
typically takes up to 17ms; up to 10.2ms for the delay and OCP
sample, and 6.8ms for the soft-start ramp.
Figure 3 shows the normal curve in blue; initialization begins
at T0, and the output ramps between T1 and T2. If the output
is pre-biased to a voltage less than the expected value, as
shown by the magenta curve, the ISL8105 will detect that
condition. Neither MOSFET will turn on until the soft-start
ramp voltage exceeds the output; V
OUT
starts seamlessly
ramping from there. If the output is pre-biased to a voltage
above the expected value, as in the red curve, neither
MOSFET will turn on until the end of the soft-start, at which
time it will pull the output voltage down to the final value. Any
resistive load connected to the output will help pull down the
voltage (at the RC rate of the R of the load and the C of the
output capacitance).
GND>
FIGURE 1. POR AND SOFT-START OPERATION
Figure 2 shows a typical power-up sequence in more detail.
The initialization starts at T0, when either V
CC
rises above
V
POR
, or the COMP/SD pin is released (after POR). The
COMP/SD will be pulled up by an internal 20µA current
source, but the timing will not begin until the COMP/SD
exceeds the V
DISABLE
trip point (at T1). The external
capacitance of the disabling device, as well as the
compensation capacitors, will determine how quickly the
20µA current source will charge the COMP/SD pin. With
typical values, it should add a small delay compared to the
soft-start times. The COMP/SD will continue to ramp to ~1V.
LGATE
STARTS
SWITCHING
COMP/SD (0.25V/DIV)
0.4V
LGATE/OCSET (0.25V/DIV)
V
OUT
(0.5V/DIV)
GND>
3.4ms
3.4ms
0 - 3.4ms
6.8ms
T0 T1
T2
T3 T4
T5
FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION
From T1, there is a nominal 6.8ms delay, which allows the V
CC
pin to exceed 6.5V (if rising up towards 12V), so that the
internal bias regulator can turn on cleanly. At the same time, the
LGATE/OCSET pin is initialized, by disabling the LGATE driver
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