3.3V MULTI-MEDIA FIFO
16 BIT V-III, 32 BIT Vx-III FAMILY
UP TO 1 Mb DENSITY
IDT72V15160
IDT72V16160
IDT72V17160
IDT72V18160
IDT72V19160
PRELIMINARY
IDT72V14320
IDT72V15320
IDT72V16320
IDT72V17320
IDT72V18320
IDT72V19320
FEATURES:
•
Choose among the following memory organizations: Commercial
V-III
Vx-III
•
•
•
•
•
•
•
•
IDT72V15160 - 4,096 x 16
IDT72V16160 - 8,192 x 16
IDT72V17160 - 16,384 x 16
IDT72V18160 - 32,768 x 16
IDT72V19160 - 65,536 x 16
IDT72V14320 - 1,024 x 32
IDT72V15320 - 2,048 x 32
IDT72V16320 - 4,096 x 32
IDT72V17320 - 8,192 x 32
IDT72V18320 - 16,384 x 32
IDT72V19320 - 32,768 x 32
•
•
•
Up to 100 MHz Operation of the Clocks
5V input tolerant
Auto power down minimizes standby power consumption
•
•
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags through serial input
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function (PBGA Only)
Available in a 80-pin (V-III) Thin Quad Flat Pack, 128-pin(Vx-III)
Thin Quad Flat Pack (TQFP) or a 144-pin (Vx-III) Plastic Ball Grid
Array (PBGA) (with additional features)
Industrial temperature range (–40°C to +85°C)
°
°
High-performance submicron CMOS technology
FUNCTIONAL BLOCK DIAGRAM
*
Available on the Vx-III PBGA package only.
MRS
WCLK
WEN
PRS
RCLK
REN
OE
D0 - Dn
Data In
x16, x32
FIFO ARRAY
Q0 - Qn
Data Out
x16, x32
WRITE
CONTROL
RESET LOGIC
READ
CONTROL
*
*
**
*
TCK
TRST
TMS
TDI
TDO
JTAG CONTROL
(BOUNDARY
SCAN)
*
LD
SEN
SI
PFM
FLAG LOGIC
FSEL1
EF
FSEL0
HF
PAE
FF
PAF
6163 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
APRIL 2003
DSC-6163/-
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTI-MEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTI-MEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
DESCRIPTION:
The IDT V-III and Vx-III Multi-Media FIFOs are exceptionally deep, high
speed, CMOS First-In-First-Out (FIFO) memories with independent clocked
read and write controls and high density offerings up to 1 Mbit.
Each FIFO has a data input port (D
n
) and a data output port (Q
n
). The
frequencies of both the RCLK (read port clock) and the WCLK (write port
clock) signals may vary from 0 to f
S
(
MAX)
with complete independence.
There are no restrictions on the frequency of the one clock input with respect
to the other.
These FIFOs have five flag pins,
EF
(Empty Flag),
FF
(Full Flag),
HF
(Half-
full Flag),
PAE
(Programmable Almost-Empty flag) and
PAF
(Programmable
Almost-Full flag).
PAE
and
PAF
can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded with the serial interface to any user desired value or by default values.
Eight default offset settings are provided, so that
PAE
can be set to switch at a
predefined number of locations from the empty boundary and the
PAF
threshold
can also be set at similar predefined values from the full boundary. The default
offset values are set during Master Reset by the state of the FSEL0, FSEL1, and
LD
pins.
For serial programming,
SEN
together with
LD
on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI).
During Master Reset (MRS) the read and write pointers are set to the first
location of the FIFO.
PIN CONFIGURATIONS (16-BIT V-III FAMILY)
WCLK
PRS
MRS
LD
SI
FF
PAF
GND
FSEL0
HF
FSEL1
GND
GND
V
CC
PAE
PFM
EF
GND
RCLK
REN
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
WEN
SEN
DNC
(1)
V
CC
DNC
(1)
GND
GND
D0
V
CC
D1
GND
D2
D3
GND
D4
D5
D6
D7
D8
V
CC
INDEX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
CC
OE
V
CC
Q0
Q1
GND
GND
DNC
(1)
Q2
V
CC
Q3
Q4
GND
Q5
GND
Q6
V
CC
Q7
Q8
Q9
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
6163 drw02
NOTE:
1. DNC = Do Not Connect.
D9
GND
GND
D10
D11
D12
D13
D14
D15
GND
Q15
Q14
GND
Q13
Q12
V
CC
Q11
Q10
GND
DNC
(1)
TQFP (PN80-1, order code: PF)
TOP VIEW
2
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTI-MEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTI-MEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the programmable flag settings existing before
Partial Reset remain unchanged.
PRS
is useful for resetting a device in mid-
operation, when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the
PAE
(Programmable Almost-
Empty flag) and
PAF
(Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the
PAE
and
PAF
flags.
If asynchronous
PAE/PAF
configuration is selected, the
PAE
is asserted
LOW on the LOW-to-HIGH transition of RCLK.
PAE
is reset to HIGH on the LOW-
to-HIGH transition of WCLK. Similarly, the
PAF
is asserted LOW on the LOW-
to-HIGH transition of WCLK and
PAF
is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous
PAE/PAF
configuration is selected , the
PAE
is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly,
PAF
is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during Master Reset by the state of the Programmable Flag
Mode (PFM) pin.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT V-III and Vx-III family of FIFOs are fabricated using IDT’s high
speed submicron CMOS technology.
PIN CONFIGURATIONS (32-BIT Vx-III FAMILY)
WCLK
PRS
MRS
LD
SI
FF
V
CC
PAF
GND
GND
FS0
HF
GND
FS1
GND
GND
GND
V
CC
PAE
PFM
EF
GND
GND
RCLK
REN
V
CC
INDEX
WEN
SEN
DNC
(1)
V
CC
DNC
(1)
GND
D0
D1
D2
D3
V
CC
D4
D5
GND
D6
D7
D8
GND
D9
D10
GND
GND
D11
V
CC
D12
D13
D14
D15
GND
D16
D17
GND
D18
D19
V
CC
D20
GND
D21
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
D22
D23
D24
D25
GND
GND
D26
D27
D28
V
CC
D29
D30
D31
GND
Q31
Q30
Q29
Q28
Q27
Q26
GND
DNC
(1)
V
CC
Q25
Q24
Q23
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
OE
V
CC
V
CC
Q0
Q1
Q2
Q3
GND
GND
Q4
Q5
Q6
Q7
Q8
DNC
(1)
V
CC
Q9
Q10
GND
GND
DNC
(1)
Q11
Q12
Q13
Q14
Q15
GND
Q16
Q17
V
CC
V
CC
DNC
(1)
Q18
Q19
Q20
GND
Q21
Q22
6163 drw03
NOTE:
1. DNC - Do Not Connect.
TQFP: (PK128-1, order code: PF)
TOP VIEW
3
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTI-MEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTI-MEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
PIN CONFIGURATIONS-CONTINUED (32-BIT VX-III FAMILY)
A1 BALL PAD CORNER
A
V
CC
WEN
WCLK
PRS
PAF
LD
FF
MRS
HF
GND
EF
RCLK
GND
PAE
REN
OE
Q0
Q1
B
SEN
GND
FS0
FS1
V
CC
PFM
V
CC
C
D0
D1
D2
SI
GND
V
CC
V
CC
GND
GND
Q3
Q2
D
D3
D4
D7
D5
D8
V
CC
V
CC
V
CC
GND
GND
GND
GND
GND
V
CC
GND
V
CC
V
CC
Q6
Q9
Q5
Q8
Q4
Q7
E
D6
F
D9
D10
D11
V
CC
V
CC
GND
GND
GND
GND
V
CC
V
CC
Q12
Q11
Q10
G
D14
D13
D12
GND
GND
GND
GND
Q13
Q14
Q15
H
D17
D16
D15
V
CC
GND
GND
GND
GND
V
CC
Q16
Q17
Q18
J
D20
D19
D18
V
CC
V
CC
GND
GND
V
CC
V
CC
Q19
Q22
Q20
Q23
Q21
K
D23
D22
D21
D28
D31
V
CC
V
CC
TDO
Q29
DNC
L
GND
GND
GND
D25
D24
D27
D26
D30
D29
TMS
TRST
TCK
TDI
Q31
Q30
Q28
Q27
Q26
Q25
DNC
Q24
DNC
DNC
M
GND
1
NOTE:
1. DNC - Do Not Connect.
2
3
4
5
6
7
8
9
10
11
12
6163 drw03b
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)
TOP VIEW
4
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTI-MEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTI-MEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
D
0
–Dn
EF
FF
FSEL0
(1)
FSEL1
(1)
HF
LD
MRS
OE
PAE
PAF
PFM
(1)
PRS
Q
0
–Qn
RCLK
REN
SEN
SI
WCLK
WEN
V
CC
GND
Name
Data Inputs
Empty Flag
Full Flag
Flag Select Bit 0
Flag Select Bit 1
Half-Full Flag
Load
I/O
I
O
O
I
I
O
I
Description
Data inputs for a 16 or 32-bit bus
EF
indicates the FIFO memory is empty. See Table 2.
FF
indicates the FIFO memory is full. See Table 2.
During Master Reset, this input along with FSEL1 and the
LD
pin, will select the default offset values for the
programmable flags
PAE
and
PAF.
There are up to eight possible settings available.
During Master Reset, this input along with FSEL0 and the
LD
pin will select the default offset values for the
programmable flags
PAE
and
PAF.
There are up to eight possible settings available.
HF
indicates the FIFO memory is more than half-full.
HF
is asserted when the number of words written into the FIFO
reaches N
÷
2+1, where N is the total depth of the FIFO. See Table 2.
During Master Reset, the state of the
LD
input along with FSEL0 and FSEL1, determines one of eight default offset
values for the
PAE
and
PAF
flags and serial programming mode. After Master Reset,
LD
must be high and should
only toggle LOW together with
SEN
to start serial loading of the flag offsets.
MRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset,
the FIFO is configured for one of eight programmable flag default settings, serial programming of the offset settings and
synchronous versus asynchronous programmable flag timing modes.
OE
controls the output line drivers
.
PAE
goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
register.
PAE
goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF
goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Full Offset register.
PAF
goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
will select Synchronous Programmable flag timing mode.
PRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
the serial programming method or programmable flag settings are all retained.
Data outputs for an 16 or 32-bit bus. Outputs are not 5V tolerant regardless of the state of
OE.
When enabled by
REN,
the rising edge of RCLK reads data from the FIFO memory.
REN
enables RCLK for reading data from the FIFO memory.
SEN
enables serial loading of programmable flag offsets.
SEN
must be high during Master Reset and should only
toggle LOW together with
LD
to start serial loading of the flag offsets.
At Maser Reset this pin is LOW. After Master Reset, this pin functions as a serial input for loading offset registers.
Enabled by
WEN,
the rising edge of WCLK writes data into the FIFO.
WEN
enables WCLK for writing data into the FIFO memory.
These are V
CC
supply inputs and must be connected to the 3.3V supply rail.
Ground Pins.
Master Reset
I
Output Enable
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Programmable
Flag Mode
Partial Reset
Data Outputs
Read Clock
Read Enable
Serial Enable
Serial In
Write Clock
Write Enable
+3.3V Supply
Ground
I
O
O
I
I
O
I
I
I
I
I
I
I
I
NOTE:
1. Inputs should not change state after Master Reset.
**Please
continue to next page for more Pin descriptions for PBGA package.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
