HB52R168DB-D
128 MB Unbuffered SDRAM S.O.DIMM
16-Mword
×
64-bit, 66 MHz Memory Bus, 1-Bank Module
(16 pcs of 16 M
×
4 components)
ADE-203-973 (Z)
Preliminary, Rev. 0.0
Nov. 6, 1998
Description
The HB52R168DB is a 16M
×
64
×
1 bank Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 16 pieces of 64-Mbit SDRAM (HM5264405DTB) sealed in TCP
package and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the
HB52R168DB is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, the
HB52R168DB makes high density mounting possible without surface mount technology.
The
HB52R168DB provides common data inputs and outputs. Decoupling capacitors are mounted beside TCP
on the module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which
would be electrical defects.
Features
•
Fully compatible with JEDEC standard outline unbuffered 8-byte S.O.DIMM
•
144-pin Zig Zag Dual tabs socket type
Outline: 67.60 mm (Length)
×
25.40 mm (Height)
×
3.80 mm (Thickness)
Lead pitch: 0.80 mm
•
3.3 V power supply
•
Clock frequency: 66 MHz
•
LVTTL interface
•
Data bus width:
×
64 Non parity
•
Single pulsed
RAS
•
4 Banks can operates simultaneously and independently
•
Burst read/write operation and burst read/single write operation capability
•
Programmable burst length : 1/2/4/8/full page
HB52R168DB-D
•
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
•
Programmable
CE
latency: 2/3
•
Byte control by DQMB
•
Refresh cycles: 4096 refresh cycles/64 ms
•
2 variations of refresh
Auto refresh
Self refresh
•
Low self refresh current: HB52R168DB-10DL (L-version)
•
Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No.
HB52R168DB-10D
HB52R168DB-10DL
Frequency
66 MHz
66 MHz
CE
latency
2/3
2/3
Package
Contact pad
Small outline DIMM (144-pin) Gold
Pin Arrangement
Front Side
1pin
2pin
59pin
60pin
61pin
62pin
143pin
144pin
Back Side
2
HB52R168DB-D
Front side
Pin No.
67
69
71
Signal name Pin No.
W
S0
NC
139
141
143
Back side
Signal name Pin No.
V
SS
SDA
V
CC
68
70
72
Signal name Pin No.
NC
NC
NC
140
142
144
Signal name
V
SS
SCL
V
CC
Pin Description
Pin name
A0 to A11
Function
Address input
Row address
A0 to A11
Column address A0 to A9
A12/A13
DQ0 to DQ63
S0
RE
CE
W
DQMB0 to DQMB7
CK0/CK1
CKE0
SDA
SCL
V
CC
V
SS
NC
Bank select address
Data-input/output
Chip select
Row address asserted bank enable
Column address asserted
Write enable
Byte input/output mask
Clock input
Clock enable
Data-input/output for serial PD
Clock input for serial PD
Power supply
Ground
No connection
BA1, BA0
4
HB52R168DB-D
Serial PD Matrix*
1
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
Number of bytes used by
module manufacturer
Total SPD memory size
Memory type
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
80
08
04
0C
0A
01
40
00
01
F0
128
256 byte
SDRAM
12
10
1
64
0 (+)
LVTTL
CL = 3
Number of row addresses bits 0
Number of column addresses
bits
Number of banks
Module data width
0
0
0
Module data width (continued) 0
Module interface signal levels 0
SDRAM cycle time
(highest
CE
latency)
15 ns
SDRAM access from Clock
(highest
CE
latency)
9 ns
Module configuration type
Refresh rate/type
1
10
1
0
0
1
0
0
0
0
90
11
12
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
80
Non parity
Normal
(15.625
µs)
Self refresh
16M
×
4
—
1 CLK
13
14
15
SDRAM width
Error checking SDRAM width
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
04
00
01
0
SDRAM device attributes:
minimum clock delay for back-
to-back random column
addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes:
number of banks on SDRAM
device
SDRAM device attributes:
CE
latency
SDRAM device attributes:
S0
latency
SDRAM device attributes:
W
latency
SDRAM module attributes
1
0
16
17
0
0
0
0
0
0
1
0
1
1
1
0
1
0
8F
04
1, 2, 4, 8, full
page
4
18
19
20
21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
06
01
01
00
2, 3
0
0
Non buffer
5