Intel
®
Xeon
®
Processor E3-1200 v3
Product Family
Datasheet – Volume 2 of 2
June 2013
Order No.: 329000-001
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death.
SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND
ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL
CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF
PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL
OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or
characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without
notice. Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling
1-800-548-4725, or go to:
http://www.intel.com/design/literature.htm
Any software source code reprinted in this document is furnished for informational purposes only and may only be used or copied and no license,
express or implied, by estoppel or otherwise, to any of the reprinted source code is granted by this document.
Any software source code reprinted in this document is furnished under a software license and may only be used or copied in accordance with the
terms of that license.
This document contains information on products in the design phase of development.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families: Go to:
http://www.intel.com/products/processor_number
Code Names are only for use by Intel to identify products, platforms, programs, services, etc. ("products") in development by Intel that have not been
made commercially available to the public, i.e., announced, launched or shipped. They are never to be used as "commercial" names for products. Also,
they are not intended to function as trademarks.
Intel
®
Hyper-Threading Technology (Intel
®
HT Technology) is available on select Intel
®
Core™ processors. It requires an Intel
®
HT Technology
enabled system. Consult your PC manufacturer. Performance will vary depending on the specific hardware and software used. Not available on Intel
®
Core™ i5-750. For more information including details on which processors support Intel
®
HT Technology, visit
http://www.intel.com/info/
hyperthreading.
Intel
®
64 architecture requires a system with a 64-bit enabled processor, chipset, BIOS and software. Performance will vary depending on the specific
hardware and software you use. Consult your PC manufacturer for more information. For more information, visit
http://www.intel.com/
content/www/us/en/architecture-and-technology/microarchitecture/intel-64-architecture-general.html.
No computer system can provide absolute security under all conditions. Intel
®
Trusted Execution Technology (Intel
®
TXT) requires a computer with
Intel
®
Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured
launched environment (MLE). Intel TXT also requires the system to contain a TPM v1.s. For more information, visit
http://www.intel.com/technology/
security.
Intel
®
Virtualization Technology (Intel
®
VT) requires a computer system with an enabled Intel
®
processor, BIOS, and virtual machine monitor (VMM).
Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be
compatible with all operating systems. Consult your PC manufacturer. For more information, visit
http://www.intel.com/go/virtualization.
Requires a system with Intel
®
Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology 2.0 are only available on select
Intel
®
processors. Consult your PC manufacturer. Performance varies depending on hardware, software, and system configuration. For more
information, visit
http://www.intel.com/go/turbo.
Requires activation and a system with a corporate network connection, an Intel® AMT-enabled chipset, network hardware and software. For
notebooks, Intel AMT may be unavailable or limited over a host OS-based VPN, when connecting wirelessly, on battery power, sleeping, hibernating or
powered off. Results dependent upon hardware, setup and configuration.
Intel, Intel Xeon, Intel vPro, Ultrabook, vPro Inside, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2013, Intel Corporation. All rights reserved.
Intel
®
Xeon
®
Processor E3-1200 v3 Product Family
Datasheet – Volume 2 of 2
2
June 2013
Order No.: 329000-001
Contents—Processor
Contents
Revision History................................................................................................................13
1.0 Introduction................................................................................................................14
2.0 Processor Configuration Registers.............................................................................. 15
2.1
2.2
2.3
2.4
2.5
Register Terminology............................................................................................ 15
PCI Devices and Functions..................................................................................... 16
System Address Map............................................................................................. 18
Legacy Address Range...........................................................................................21
Main Memory Address Range (1 MB – TOLUD).......................................................... 24
2.5.1 GFX Stolen Spaces.................................................................................... 27
2.5.2 Intel
®
Management Engine (Intel
®
ME) UMA................................................ 28
2.6 PCI Memory Address Range (TOLUD – 4 GB)............................................................ 28
2.7 Main Memory Address Space (4 GB to TOUUD)......................................................... 31
2.7.1 Programming Model.................................................................................. 34
2.8 PCI Express* Configuration Address Space............................................................... 39
2.9 PCI Express* Graphics Attach (PEG)........................................................................ 39
2.10 Graphics Memory Address Ranges......................................................................... 40
2.11 System Management Mode (SMM)........................................................................41
2.12 SMM and VGA Access Through GTT TLB.................................................................41
2.13 Intel
®
Management Engine (Intel
®
ME) Stolen Memory Accesses..............................41
2.14 I/O Address Space............................................................................................. 42
2.15 Direct Media Interface (DMI) Interface Decode Rules.............................................. 43
2.16 PCI Express* Interface Decode Rules.................................................................... 46
2.17 Legacy VGA and I/O Range Decode Rules.............................................................. 47
2.18 I/O Mapped Registers......................................................................................... 50
3.1 Host Bridge/DRAM Registers Summary.................................................................... 51
3.1.1 VID—Vendor Identification......................................................................... 52
3.1.2 DID—Device Identification..........................................................................52
3.1.3 PCICMD—PCI Command............................................................................ 53
3.1.4 PCISTS—PCI Status.................................................................................. 54
3.1.5 RID—Revision Identification....................................................................... 55
3.1.6 CC—Class Code........................................................................................ 55
3.1.7 HDR—Header Type....................................................................................56
3.1.8 SVID—Subsystem Vendor Identification....................................................... 56
3.1.9 SID—Subsystem Identification....................................................................56
3.1.10 CAPPTR—Capabilities Pointer.................................................................... 56
3.1.11 PXPEPBAR—PCI Express Egress Port Base Address.......................................56
3.1.12 MCHBAR—Host Memory Mapped Register Range Base.................................. 57
3.1.13 GGC—GMCH Graphics Control Register.......................................................58
3.1.14 DEVEN—Device Enable.............................................................................59
3.1.15 PAVPC—Protected Audio Video Path Control................................................ 60
3.1.16 DPR—DMA Protected Range......................................................................61
3.1.17 PCIEXBAR—PCI Express Register Range Base Address..................................61
3.1.18 DMIBAR—Root Complex Register Range Base Address................................. 62
3.1.19 MESEG—Manageability Engine Base Address Register...................................63
3.0 Host Device Configuration Registers........................................................................... 51
June 2013
Order No.: 329000-001
Intel
®
Xeon
®
Processor E3-1200 v3 Product Family
Datasheet – Volume 2 of 2
3
Processor—Contents
3.1.20 MESEG—Manageability Engine Limit Address Register.................................. 63
3.1.21 PAM0—Programmable Attribute Map 0....................................................... 64
3.1.22 PAM1—Programmable Attribute Map 1....................................................... 65
3.1.23 PAM2—Programmable Attribute Map 2....................................................... 66
3.1.24 PAM3—Programmable Attribute Map 3....................................................... 66
3.1.25 PAM4—Programmable Attribute Map 4....................................................... 67
3.1.26 PAM5—Programmable Attribute Map 5....................................................... 68
3.1.27 PAM6—Programmable Attribute Map 6....................................................... 69
3.1.28 LAC—Legacy Access Control..................................................................... 70
3.1.29 SMRAMC—System Management RAM Control.............................................. 72
3.1.30 REMAPBASE—Remap Base Address Register............................................... 73
3.1.31 REMAPLIMIT—Remap Limit Address Register...............................................73
3.1.32 TOM—Top of Memory...............................................................................74
3.1.33 TOUUD—Top of Upper Usable DRAM.......................................................... 74
3.1.34 BDSM—Base Data of Stolen Memory..........................................................75
3.1.35 BGSM—Base of GTT stolen Memory........................................................... 76
3.1.36 TSEGMB—TSEG Memory Base...................................................................76
3.1.37 TOLUD—Top of Low Usable DRAM..............................................................76
3.1.38 ERRSTS—Error Status..............................................................................77
3.1.39 ERRCMD—Error Command........................................................................78
3.1.40 SMICMD—SMI Command......................................................................... 79
3.1.41 SCICMD—SCI Command.......................................................................... 79
3.1.42 SKPD—Scratchpad Data........................................................................... 80
3.1.43 CAPID0—Capabilities A............................................................................ 80
3.1.44 CAPID0—Capabilities B............................................................................ 81
3.2 PCI Express Controller (x16) Registers Summary...................................................... 82
3.2.1 VID—Vendor Identification......................................................................... 83
3.2.2 DID—Device Identification..........................................................................84
3.2.3 PCICMD—PCI Command............................................................................ 84
3.2.4 PCISTS—PCI Status.................................................................................. 85
3.2.5 RID—Revision Identification....................................................................... 87
3.2.6 CC—Class Code........................................................................................ 88
3.2.7 CL—Cache Line Size.................................................................................. 88
3.2.8 HDR—Header Type....................................................................................88
3.2.9 PBUSN—Primary Bus Number..................................................................... 89
3.2.10 SBUSN—Secondary Bus Number............................................................... 89
3.2.11 SUBUSN—Subordinate Bus Number........................................................... 89
3.2.12 IOBASE—I/O Base Address.......................................................................89
3.2.13 IOLIMIT—I/O Limit Address...................................................................... 90
3.2.14 SSTS—Secondary Status..........................................................................90
3.2.15 MBASE—Memory Base Address................................................................. 91
3.2.16 MLIMIT—Memory Limit Address................................................................ 91
3.2.17 PMBASE—Prefetchable Memory Base Address............................................. 92
3.2.18 PMLIMIT—Prefetchable Memory Limit Address.............................................93
3.2.19 PMBASEU—Prefetchable Memory Base Address Upper.................................. 93
3.2.20 PMLIMITU—Prefetchable Memory Limit Address Upper..................................94
3.2.21 CAPPTR—Capabilities Pointer.................................................................... 94
3.2.22 INTRLINE—Interrupt Line......................................................................... 94
3.2.23 INTRPIN—Interrupt Pin............................................................................ 95
3.2.24 BCTRL—Bridge Control.............................................................................95
3.2.25 PM—Power Management Capabilities..........................................................96
Intel
®
Xeon
®
Processor E3-1200 v3 Product Family
Datasheet – Volume 2 of 2
4
June 2013
Order No.: 329000-001
Contents—Processor
3.2.26 PM—Power Management Control/Status..................................................... 97
3.2.27 SS—Subsystem ID and Vendor ID Capabilities............................................ 99
3.2.28 SS—Subsystem ID and Subsystem Vendor ID............................................. 99
3.2.29 MSI—Message Signaled Interrupts Capability ID..........................................99
3.2.30 MC—Message Control.............................................................................100
3.2.31 MA—Message Address............................................................................101
3.2.32 MD—Message Data................................................................................ 101
3.2.33 PEG—PCI Express-G Capability List.......................................................... 101
3.2.34 PEG—PCI Express-G Capabilities..............................................................101
3.2.35 DCAP—Device Capabilities...................................................................... 102
3.2.36 DCTL—Device Control............................................................................ 102
3.2.37 DSTS—Device Status............................................................................. 104
3.2.38 LCTL—Link Control................................................................................ 105
3.2.39 LSTS—Link Status................................................................................. 106
3.2.40 SLOTCAP—Slot Capabilities..................................................................... 108
3.2.41 SLOTCTL—Slot Control........................................................................... 109
3.2.42 SLOTSTS—Slot Status............................................................................111
3.2.43 RCTL—Root Control............................................................................... 112
3.2.44 RSTS—Root Status................................................................................ 113
3.2.45 DCAP2—Device Capabilites 2.................................................................. 114
3.2.46 DCTL2—Device Control 2........................................................................ 116
3.2.47 LCTL2—Link Control 2............................................................................ 117
3.2.48 LSTS2—Link Status 2.............................................................................119
3.2.49 PVCCAP1—Port VC Capability Register 1................................................... 120
3.2.50 PVCCAP2—Port VC Capability Register 2................................................... 121
3.2.51 PVCCTL—Port VC Control........................................................................121
3.2.52 VC0RCAP—VC0 Resource Capability......................................................... 121
3.2.53 VC0RCTL—VC0 Resource Control............................................................. 122
3.2.54 VC0RSTS—VC0 Resource Status.............................................................. 123
3.3 PCI Express Controller (x8) Registers Summary...................................................... 123
3.3.1 VID—Vendor Identification....................................................................... 125
3.3.2 DID—Device Identification........................................................................125
3.3.3 PCICMD—PCI Command...........................................................................126
3.3.4 PCISTS—PCI Status.................................................................................127
3.3.5 RID—Revision Identification......................................................................129
3.3.6 CC—Class Code.......................................................................................129
3.3.7 CL—Cache Line Size................................................................................ 130
3.3.8 HDR—Header Type.................................................................................. 130
3.3.9 PBUSN—Primary Bus Number................................................................... 130
3.3.10 SBUSN—Secondary Bus Number..............................................................130
3.3.11 SUBUSN—Subordinate Bus Number......................................................... 131
3.3.12 IOBASE—I/O Base Address..................................................................... 131
3.3.13 IOLIMIT—I/O Limit Address.................................................................... 131
3.3.14 SSTS—Secondary Status........................................................................ 132
3.3.15 MBASE—Memory Base Address............................................................... 132
3.3.16 MLIMIT—Memory Limit Address...............................................................133
3.3.17 PMBASE—Prefetchable Memory Base Address............................................133
3.3.18 PMLIMIT—Prefetchable Memory Limit Address........................................... 134
3.3.19 PMBASEU—Prefetchable Memory Base Address Upper................................ 134
3.3.20 PMLIMITU—Prefetchable Memory Limit Address Upper................................ 135
3.3.21 CAPPTR—Capabilities Pointer...................................................................135
June 2013
Order No.: 329000-001
Intel
®
Xeon
®
Processor E3-1200 v3 Product Family
Datasheet – Volume 2 of 2
5
Linux开发
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
