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HYB18H512321BF-08: 产品描述Synchronous Graphics RAM, 16MX32, 0.2ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136; 产品类别存储存储; 文件大小2MB，共40页; 制造商QIMONDA; 标准

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HYB18H512321BF-08概述

Synchronous Graphics RAM, 16MX32, 0.2ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136

HYB18H512321BF-08规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	QIMONDA
零件包装代码	DSBGA
包装说明	TFBGA, BGA136,12X17,32
针数	136
Reach Compliance Code	unknown
ECCN代码	EAR99
访问模式	MULTI BANK PAGE BURST
最长访问时间	0.2 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	1200 MHz
I/O 类型	COMMON
JESD-30 代码	R-PBGA-B136
长度	14 mm
内存密度	536870912 bit
内存集成电路类型	SYNCHRONOUS GRAPHICS RAM
内存宽度	32
功能数量	1
端口数量	1
端子数量	136
字数	16777216 words
字数代码	16000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度
组织	16MX32
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	TFBGA
封装等效代码	BGA136,12X17,32
封装形状	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH
电源	2 V
认证状态	Not Qualified
刷新周期	8192
座面最大高度	1.2 mm
自我刷新	YES
连续突发长度	4,8
最大待机电流	0.41 A
最大压摆率	0.92 mA
最大供电电压 (Vsup)	2.1 V
最小供电电压 (Vsup)	1.9 V
标称供电电压 (Vsup)	2 V
表面贴装	YES
技术	CMOS
温度等级	OTHER
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
宽度	10 mm

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December 2007

HYB18H512321BF–11/12/14

HYB18H512321BF–08/10

512-Mbit GDDR3 Graphics RAM

GDDR3 Graphics RAM

RoHS compliant

Internet Data Sheet

Rev. 1.3

Internet Data Sheet

HYB18H512321BF

512-Mbit GDDR3

1.2

Description

The Qimonda 512-Mbit GDDR3 Graphics RAM is a high speed memory device, designed for high bandwidth intensive

applications like PC graphics systems. The chip’s 8 bank architecture is optimized for high speed.

HYB18H512321BF uses a double data rate interface and a 4

-pre fetch architecture. The GDDR3 interface transfers two 32

bit wide data words per clock cycle to/from the I/O pins. Corresponding to the 4

-pre fetch a single write or read access consists

of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, one-half-clock-

cycle data transfers at the I/O pins.

Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively

in order to capture data properly at the receivers of both the Graphics SDRAM and the controller. Data strobes are organized

per byte of the 32 bit wide interface. For read commands the RDQS are edge-aligned with data, and the WDQS are center-

aligned with data for write commands.

The HYB18H512321BF operates from a differential clock (CLK and CLK). Commands (addresses and control signals) are

registered at every positive edge of CLK. Input data is registered on both edges of WDQS, and output data is referenced to

both edges of RDQS.

In this document references to “the positive edge of CLK” imply the crossing of the positive edge of CLK and the negative edge

of CLK. Similarly, the “negative edge of CLK” refers to the crossing of the negative edge of CLK and the positive edge of CLK.

References to RDQS are to be interpreted as any or all RDQS<3:0>. WDQS, DM and DQ should be interpreted in a similar

fashion.

Read and write accesses to the HYB18H512321BF are burst oriented. The burst length is fixed to 4 and 8 and the two least

significant bits of the burst address are “Don’t Care” and internally set to LOW. Accesses begin with the registration of an

ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVATE command are used to select the bank and the row to be accessed. The address bits registered coincident with the

READ or WRITE command are used to select the bank and the column location for the burst access. Each of the 8 banks

consists of 4096 row locations and 512 column locations. An AUTO PRECHARGE function can be combined with READ and

WRITE to provide a self-timed row precharge that is initiated at the end of the burst access. The pipe lined, multibank

architecture of the HYB18H512321BF allows for concurrent operation, thereby providing high effective bandwidth by hiding row

precharge and activation time.

The “On Die Termination” interface (ODT) is optimized for high frequency digital data transfers and is internally controlled. The

termination resistor value can be set using an external ZQ resistor or disabled through the Extended Mode Register.

The output driver impedance can be set using the Extended Mode Register. It can either be set to ZQ / 6 (auto calibration) or

to 35, 40 or 45 Ohms.

Auto Refresh and Power Down with Self Refresh operations are supported.

An industrial standard PG–TFBGA–136 package is used which enables ultra high speed data transfer rates and a simple

upgrade path from former DDR Graphics SDRAM products.

Rev. 1.3, 2007-12

05292007-WAU2-UU95

HYB18H512321BF-08相似产品对比

	HYB18H512321BF-08	HYB18H512321BF-11	HYB18H512321BF-12	HYB18H512321BF-10	HYB18H512321BF-14
描述	Synchronous Graphics RAM, 16MX32, 0.2ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136	Synchronous Graphics RAM, 16MX32, 0.22ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136	Synchronous Graphics RAM, 16MX32, 0.22ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136	Synchronous Graphics RAM, 16MX32, 0.21ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136	Synchronous Graphics RAM, 16MX32, 0.25ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136
是否Rohs认证	符合	符合	符合	符合	符合
零件包装代码	DSBGA	DSBGA	DSBGA	DSBGA	DSBGA
包装说明	TFBGA, BGA136,12X17,32	TFBGA, BGA136,12X17,32	TFBGA, BGA136,12X17,32	TFBGA, BGA136,12X17,32	TFBGA, BGA136,12X17,32
针数	136	136	136	136	136
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
最长访问时间	0.2 ns	0.22 ns	0.22 ns	0.21 ns	0.25 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	1200 MHz	900 MHz	800 MHz	1000 MHz	700 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PBGA-B136	R-PBGA-B136	R-PBGA-B136	R-PBGA-B136	R-PBGA-B136
长度	14 mm	14 mm	14 mm	14 mm	14 mm
内存密度	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit
内存集成电路类型	SYNCHRONOUS GRAPHICS RAM	SYNCHRONOUS GRAPHICS RAM	SYNCHRONOUS GRAPHICS RAM	SYNCHRONOUS GRAPHICS RAM	SYNCHRONOUS GRAPHICS RAM
内存宽度	32	32	32	32	32
功能数量	1	1	1	1	1
端口数量	1	1	1	1	1
端子数量	136	136	136	136	136
字数	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words
字数代码	16000000	16000000	16000000	16000000	16000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C
组织	16MX32	16MX32	16MX32	16MX32	16MX32
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
封装等效代码	BGA136,12X17,32	BGA136,12X17,32	BGA136,12X17,32	BGA136,12X17,32	BGA136,12X17,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
电源	2 V	1.8 V	1.8 V	2 V	1.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	8192	8192	8192	8192	8192
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	YES	YES	YES	YES	YES
连续突发长度	4,8	4,8	4,8	4,8	4,8
最大待机电流	0.41 A	0.35 A	0.32 A	0.38 A	0.235 A
最大压摆率	0.92 mA	0.8 mA	0.74 mA	0.86 mA	0.68 mA
最大供电电压 (Vsup)	2.1 V	1.9 V	1.9 V	2.1 V	1.9 V
最小供电电压 (Vsup)	1.9 V	1.7 V	1.7 V	1.9 V	1.7 V
标称供电电压 (Vsup)	2 V	1.8 V	1.8 V	2 V	1.8 V
表面贴装	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	OTHER	OTHER	OTHER	OTHER	OTHER
端子形式	BALL	BALL	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	10 mm	10 mm	10 mm	10 mm	10 mm
厂商名称	QIMONDA	-	QIMONDA	QIMONDA	QIMONDA

HYB18H512321BF-08

HYB18H512321BF-08概述

HYB18H512321BF-08规格参数

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