Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
DESCRIPTION
Monolithic temperature and
overload protected logic level power
MOSFET in
TOPFET2
technology
assembled in a 3 pin surface mount
plastic package.
BUK127-50GT
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
D
T
j
R
DS(ON)
PARAMETER
Continuous drain source voltage
Continuous drain current
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
MAX.
50
2.1
1.8
150
200
UNIT
V
A
W
˚C
mΩ
APPLICATIONS
General purpose switch for driving
lamps
motors
solenoids
heaters
in automotive systems and other
applications.
FEATURES
TrenchMOS output stage
Current trip protection
Overload protection
Overtemperature protection
Protection latched reset by input
5 V logic compatible input level
Control of output stage
and supply of overload
protection circuits
derived from input
Low operating input current
permits direct drive by
micro-controller
ESD protection on all pins
Overvoltage clamping for turn
off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
DRAIN
O/V
CLAMP
INPUT
RIG
POWER
MOSFET
LOGIC AND
PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT223
PIN
1
2
3
4
input
drain
source
drain (tab)
DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
D
TOPFET
I
P
1
2
3
S
December 2001
1
Rev 2.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
I
D
I
D
I
I
I
IRM
P
D
T
stg
T
j
PARAMETER
Continuous drain source voltage
1
Drain current
2
Continuous drain current
Continuous input current
Non-repetitive peak input current
Total power dissipation
Storage temperature
Continuous junction temperature
CONDITIONS
-
-
T
a
= 25˚C
clamping
t
p
≤
1 ms
T
a
= 25 ˚C
-
normal operation
3
MIN.
-
-
-
-
-
-
-55
-
BUK127-50GT
MAX.
50
current trip
2.1
3
10
1.8
150
150
UNIT
V
A
A
mA
mA
W
˚C
˚C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model;
C = 250 pF; R = 1.5 kΩ
MIN.
-
MAX.
2
UNIT
kV
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL
E
DSM
E
DRM
PARAMETER
Non-repetitive clamping energy
Repetitive clamping energy
CONDITIONS
T
a
≤
25 ˚C; I
DM
≤
I
D(TO)
;
inductive load
T
sp
≤
125 ˚C; I
DM
= 1 A;
f = 250 Hz
MIN.
-
-
MAX.
100
5
UNIT
mJ
mJ
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads.
Overload protection operates by means of drain current trip or by activating the overtemperature protection.
SYMBOL
V
DDP
PARAMETER
REQUIRED CONDITION
MIN.
-
MAX.
35
UNIT
V
Protected drain source supply voltage V
IS
≥
4 V
THERMAL CHARACTERISTICS
SYMBOL
R
th j-sp
R
th j-b
R
th j-a
PARAMETER
Thermal resistance
Junction to solder point
Junction to board
4
Junction to ambient
CONDITIONS
MIN.
-
-
-
TYP.
12
40
-
MAX.
18
-
70
UNIT
K/W
K/W
K/W
Mounted on any PCB
Mounted on PCB of fig. 4
1
Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2
Refer to OVERLOAD PROTECTION CHARACTERISTICS.
3 Not
in an overload condition with drain current limiting.
4
Temperature measured 1.3 mm from tab.
December 2001
2
Rev 2.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
OUTPUT CHARACTERISTICS
Limits are for -40˚C
≤
T
mb
≤
150˚C; typicals are for T
mb
= 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
Off-state
V
(CL)DSS
I
DSS
Drain-source clamping voltage
CONDITIONS
V
IS
= 0 V
I
D
= 10 mA
I
D
= 200 mA; t
p
≤
300
µs; δ ≤
0.01
Drain source leakage current
On-state
R
DS(ON)
Drain-source resistance
V
DS
= 40 V
T
mb
= 25 ˚C
V
IS
≥
4 V; t
p
≤
300
µs; δ ≤
0.01
I
D
= 100 mA
T
mb
= 25 ˚C
-
-
50
50
-
-
MIN.
BUK127-50GT
TYP.
MAX.
UNIT
-
60
-
0.1
-
70
100
10
V
V
µA
µA
mΩ
mΩ
-
150
380
200
INPUT CHARACTERISTICS
The supply for the logic and overload protection is taken from the input.
Limits are for -40˚C
≤
T
mb
≤
150˚C; typicals are for T
mb
= 25˚C unless otherwise specified
SYMBOL
V
IS(TO)
I
IS
I
ISL
V
ISR
t
lr
V
(CL)IS
R
IG
PARAMETER
Input threshold voltage
Input supply current
Input supply current
Protection reset voltage
1
Latch reset time
Input clamping voltage
Input series resistance
2
to gate of power MOSFET
CONDITIONS
V
DS
= 5 V; I
D
= 1 mA
T
mb
= 25˚C
normal operation;
protection latched;
reset time t
r
≥
100
µs
V
IS1
= 5 V, V
IS2
< 1 V
I
I
= 1.5 mA
T
mb
= 25˚C
V
IS
= 5 V
V
IS
= 4 V
V
IS
= 5 V
V
IS
= 3 V
MIN.
0.6
1.1
100
80
1.4
0.7
1.5
10
5.5
-
TYP.
-
1.6
220
195
2
1.1
2
40
-
2.5
MAX.
2.4
2.1
400
330
2.5
1.5
2.5
100
8.5
-
UNIT
V
V
µA
µA
mA
mA
V
µs
V
kΩ
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off to protect itself when one of the overload thresholds is exceeded. It remains latched off until
reset by the input.
SYMBOL
I
D(TO)
PARAMETER
Overload protection
Drain current trip threshold
CONDITIONS
V
IS
= 4 V to 5.5 V
T
j
= 25˚C
-40˚C
≤
T
j
≤
150˚C
Overtemperature protection
T
j(TO)
Threshold junction temperature V
IS
= 4 V to 5.5 V
150
170
-
˚C
4
3
-
-
8
9
A
A
MIN.
TYP.
MAX.
UNIT
1
The input voltage below which the overload protection circuits will be reset.
2
Not directly measureable from device terminals.
December 2001
3
Rev 2.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
SWITCHING CHARACTERISTICS
BUK127-50GT
T
a
= 25 ˚C; resistive load R
L
= 50
Ω;
adjust V
DD
to obtain I
D
= 250 mA; refer to test circuit and waveforms
SYMBOL
t
d on
t
r
t
d off
t
f
PARAMETER
Turn-on delay time
Rise time
Turn-off delay time
Fall time
V
IS
= 5 V to V
IS
= 0 V
CONDITIONS
V
IS
= 0 V to V
IS
= 5 V
MIN.
-
-
-
-
TYP.
0.5
0.7
3.2
1.6
MAX.
0.9
1.5
6.5
3.5
UNIT
µs
µs
µs
µs
REVERSE DIODE LIMITING VALUE
SYMBOL
I
S
PARAMETER
Continuous forward current
CONDITIONS
T
mb
≤
25 ˚C; V
IS
= 0 V
MIN.
-
MAX.
2
UNIT
A
REVERSE DIODE CHARACTERISTICS
Limits are for -40˚C
≤
T
mb
≤
150˚C; typicals are for T
mb
= 25˚C unless otherwise specified
SYMBOL
V
SDO
t
rr
PARAMETER
Forward voltage
Reverse recovery time
CONDITIONS
I
S
= 2 A; V
IS
= 0 V; t
p
= 300
µs
not applicable
1
MIN.
-
-
TYP.
0.83
-
MAX.
1.1
-
UNIT
V
-
1
The reverse diode of this type is not intended for applications requiring fast reverse recovery.
December 2001
4
Rev 2.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
MECHANICAL DATA
Plastic surface mounted package; collector pad for good heat transfer; 4 leads
BUK127-50GT
SOT223
D
B
E
A
X
c
y
H
E
b
1
v
M
A
4
Q
A
A
1
1
e
1
e
2
b
p
3
w
M
B
detail X
L
p
0
2
scale
4 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
1.8
1.5
A
1
0.10
0.01
b
p
0.80
0.60
b
1
3.1
2.9
c
0.32
0.22
D
6.7
6.3
E
3.7
3.3
e
4.6
e
1
2.3
H
E
7.3
6.7
L
p
1.1
0.7
Q
0.95
0.85
v
0.2
w
0.1
y
0.1
OUTLINE
VERSION
SOT223
REFERENCES
IEC
JEDEC
EIAJ
SC-73
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
99-09-13
Fig.2. SOT223 surface mounting package
1
.
1
For further information, refer to surface mounting instructions for SOT223 envelope. Epoxy meets UL94 V0 at 1/8". Net Mass: 0.11 g
December 2001
5
Rev 2.000
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