Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
DESCRIPTION
HY5DU(V)1294022-75/80/10, HY5DU(V)1298022-75/80/10 and HY5DU(V)1291623-75/80/10 are high speed
2.5V(U-part) and 3.3V(V-part) (I/O VDDQ=2.5V for all U,V-parts) 128M Double Data Rate(DDR) Synchronous
DRAM’s fabricated with the Hyundai high performance CMOS process. While all address and control inputs
are latched on the rising edge of the clock(falling edge of the /clock), data, data strobe and data mask inputs
are sampled on both rising and falling edge of the clock. The data path is internally pipelined and 2-bit pre-
fetched to achieve higher bandwidth. Because data rate is doubled through reading and writing at both rising
and falling edge of the clock, 2X higher data bandwidth can be achieved.
FEATURES
- 2.5V VDD(U-part), 3.3V VDD(V-part) and 2.5V VDDQ power supply for both parts
- Internal 4 banks with single pulsed RAS
- Fully differential clock operation with clock frequency 100MHz/125MHz/133MHz
- Data output on data strobe(DQS) edge when read (edged DQ)
- Data input on data strobe(DQS) center when write (centered DQ)
- Data strobe synchronized with output data for read and input data for write
- Programmable CAS latency 2.0/2.5/3.0 supported
- Programmable burst length 2/4/8 with both sequential and interleave mode
- Delay Locked Loop(DLL) installed with DLL reset mode
- SSTL_2 interface for all inputs and outputs
- Write mask byte control with LDM and UDM
- Bytewide data strobe with LDQS and UDQS
- Auto refresh and self refresh supported
- 4K/64ms refresh cycle
- 400mil 66 pin 0.65mm pin pitch TSOP-II package
Write Data Register
2-bit Prefetch Unit
32
Input Buffer
BLOCK DIAGRAM (x16)
16
DS
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
DM
Command
Decoder
2M x 16/ Bank 1
2M x 16/ Bank 2
2M x 16/ Bank 3
Row
Decoder
32
16
Output Buffer
Bank
Control
Sense Amplifier
2M x 16/ Bank 0
2-bit Prefetch Unit
DQ[0:15]
Mode
Register
Column Decoder
CLK_DLL
DQS
Data Strobe
Transmitter
A0-11
BA0-1
Address
Buffer
Column Address
Counter
DLL
Block
CLK
Mode Register
DS
Data Strobe
Receiver
Sep., 98
Rev. 0-A
page 1 of 28
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
ORDERING INFORMATION
HY 5D U 129 40 2 2
HYUNDAI
Memory Products
PRODUCT GROUP
55 - FP DRAM
56 - EDO DRAM
57 - SDRAM
5D - DDR SDRAM
L TC - 10
SPEED
75 - 7.5ns(133MHz)
80 - 8ns(125MHz)
10 - 10ns(100MHz)
12 - 12ns(83MHz)
15 - 15ns(66MHz)
10P - PC/100, CL=2/3
10S - PC/100, CL=2
PROCESS & POWER SUPPLY
BLANK - CMOS 5.0V VDD
V
- CMOS 3.3V VDD
U
- CMOS 2.5V VDD
PACKAGE
JC - 400mil SOJ
TC - 400mil TSOP-II
POWER CONSUMPTION
DENSITY & REFRESH CYCLE
64 - 64M bits, 8K refresh
65 - 64M bits, 4K refresh
128 - 128M bits, 8K refresh
129 - 128M bits, 4K refresh
DATA WIDTH
40 - x4
80 - x8
16 - x16
32 - x32
NUMBER OF BANKS
1 - 2 banks
2 - 4 banks
BLANK - Normal
L
- Low power
DIE GENERATION
BLANK - 1st Gen.
A
- 2nd Gen.
B
- 3rd Gen.
C
- 4th Gen.
INTERFACE
0 - LVTTL
1 - SSTL-3
2 - SSTL-2
3 - Mixed Interface
Sep., 98
Rev. 0-A
page 2 of 28
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
PIN CONFIGURATION & DESCRIPTION
x4
x8
x16
VDD
VDD
VDD
DQ0
DQ0
NC
VDDQ
VDDQ
VDDQ
DQ1
NC
NC
DQ2
DQ1
DQ0
VSSQ
VSSQ
VSSQ
DQ3
NC
NC
DQ4
DQ2
NC
VDDQ
VDDQ
VDDQ
DQ5
NC
NC
DQ6
DQ3
DQ1
VSSQ
VSSQ
VSSQ
DQ7
NC
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
LDQS
NC
NC
NC
NC
NC
VDD
VDD
VDD
NC, /QFC NC, /QFC NC, /QFC
LDM
NC
NC
/WE
/WE
/WE
/CAS
/CAS
/CAS
/RAS
/RAS
/RAS
/CS
/CS
/CS
NC
NC
NC
BA0
BA0
BA0
BA1
BA1
BA1
A10/AP A10/AP A10/AP
A0
A0
A0
A1
A1
A1
A2
A2
A2
A3
A3
A3
VDD
VDD
VDD
Pin
A0 - A11
BA0, BA1
DQ0 - DQ15
/CS
/RAS
/CAS
/WE
LDM, UDM
CLK, /CLK
CKE
LDQS, UDQS
VREF
VDD, VSS
VDDQ, VSSQ
/QFC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
TOP VIEW
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
400mil X 875mil
66 Pin TSOP-II
Pin Pitch = 0.65mm
( Normal Bend )
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Description
Row / Column Address
Bank Select Address
Data Input/Output
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Write Mask(Lower/Upper Byte)
Clock Input
Clock Enable
Data Strobe(Lower/Upper Byte)
Reference Voltage
Power, Ground
I/O Power, I/O Ground
DQ FET Switch Control(optional)
No Connection
Sep., 98
Rev. 0-A
page 3 of 28
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
ADDRESS MAPPING TABLE
Organization
x4
x8
x16
Bank Select
BA0, BA1
BA0, BA1
BA0, BA1
Row Address
A0 ~ A11
A0 ~ A11
A0 ~ A11
Column Address
A0~A9, A11
A0~A9
A0~A8
Autoprecharge
A10
A10
A10
COMMAND TRUTH TABLE
Function
Device Deselect
No Operation
Read
Read w/ Autoprecharge
Write
Write w/ Autoprecharge
Bank Activate
Precharge Selected Bank
Precharge All Banks
Read Burst Stop
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Power Down Entry
Power Down Exit
Mode Register Set
Symbol
DSEL
NOP
READ
READAP
WRITE
WRITEAP
ACT
PRE
PALL
BST
AREF
SREF
SREX
PDEN
PDEX
MRS
CKE
n-1
CKE
n
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
H
L
H
L
H
X
/CS
H
L
L
L
L
L
L
L
L
L
L
L
H
X
H
L
/RAS /CAS /WE
X
H
H
H
H
H
L
L
L
H
L
L
X
X
X
L
X
H
L
L
L
L
H
H
H
H
L
L
X
X
X
L
X
H
H
H
L
L
H
L
L
L
H
H
X
X
X
L
A11
X
X
V
V
V
V
V
X
X
X
X
X
X
X
X
L
A10
X
X
L
H
L
H
V
L
H
X
X
X
X
X
X
L
BA
X
X
V
V
V
V
V
V
X
X
X
X
X
X
X
V
A9-0
X
X
V
V
V
V
V
X
X
X
X
X
X
X
X
V
WRITE DATA MASK TRUTH TABLE
Function
Data Write/Output Enable
Data Mask/Output Disable
Upper Byte Write Enable / Lower Byte Mask
Lower Byte Write Enable / Upper Byte Mask
CKE
n-1
H
H
H
H
CKE
n
X
X
X
X
UDM
L
H
L
H
LDM
L
H
H
L
Notes : ‘ - Logic High Level, ‘ - Logic Low Level, ‘ - Don’ Care, ‘ - Valid Data Input
H’
L’
X’
t
V’
Sep., 98
Rev. 0-A
page 4 of 28
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
