VRAM
Austin Semiconductor, Inc.
262144 x 16 BIT VRAM
MULTIPORT VIDEO RAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• Military Processing Flow(SM Level)
• -55C to 125C temperature
(Top View)
64-Pin Ceramic Flatpack (HKC)
SM55161A
Production
PIN ASSIGNMENT
FEATURES
• Organization:
– DRAM: 262 144 by 16 Bits
– SAM: 512 by 16 Bits
• Dual-Port Accessibility – Simultaneous and Asynchronous
Access From the DRAM and SAM Ports
• Bidirectional Data-Transfer Function From the DRAM to
the Serial-Data Register, and from Serial Data Register to DRAM
• (8 x 8) x 2 Block Write feature for fast area fill
• Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two
Write-Per-Bit Modes to Simplify System Design
• Byte-Write Control (CASL, CASU) Provides Flexibility
• Extended Data Output for Faster System Cycle Time
• Enhanced Page-Mode Operation for Faster Access
• CAS-Before-RAS (CBR) and Hidden-Refresh Modes
• Long Refresh Period: Every 8 ms (Maximum)
• Up to 50-MHz Uninterrupted Serial-Data Streams
• 512 Selectable Serial-Register Starting Locations
• SE-Controlled Register-Status QSF
• Split-Register-Transfer Read for Simplified Real-Time Register
Load
• Programmable Split-Register Stop Point
• 3-State Serial Outputs Allow Easy Multiplexing of Video-Data
Streams
• Pin-out Compatible upgrade from SM55161
• Compatible With JEDEC Standards
PIN DESCRIPTIONS
PIN
A0-A8
CASL\, CASU\
DQ0-DQ15
DSF
NC/GND
DESCRIPTION
Address inputs
Column-Address Strobe/Byte Selects
DRAM Data I/O, Write Mask Data
Special Function Select
Special-Function Select
No Connect/Ground (NOTE: Not
connected internally to V
SS
)
Special-Function Output
Row-Address Strobe
Serial Clock
Serial Enable
Serial-Data Output
Output Enable, Transfer Select
5V Supply (TYP)
Ground
DRAM Write-Enable Select
OPTIONS
• Timing
70ns access
75ns access
80ns access
• Package
68 pin PGA
64 pin Flatpack
• Operating Temperature Ranges
- Military (-55
o
C to +125
o
C)
- Industrial (-40
o
C to +85
o
C)
MARKING
-70
-75
-80
QSF
RAS\
SC
SE\
SQ0-SQ15
TRG\
V
CC
GB
HKC
V
SS
WE\
M suffix
I suffix
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SMJ55161A
Rev. 1.6 03/05
1
VRAM
Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The SMJ55161A, a multiport-video random-access memory
(RAM), is a high-speed, dual-port memory device. It consists
of a dynamic RAM (DRAM) module organized as 262 144 words
of 16 bits each interfaced to a serial-data register (serial-access
memory [SAM]) organized as 512 words of 16 bits each. The
SMJ55161A supports three basic types of operation: random
access to and from the DRAM, serial access to/from the serial
register, and transfer of data from any row in the DRAM to the
serial register and vice versa. Except during transfer operations,
the SMJ55161A can be accessed simultaneously and
asynchronously from the DRAM and SAM ports.
The SMJ55161A is equipped with several features designed
to provide higher system-level bandwidth and to simplify design
integration on both the DRAM and SAM ports. On the DRAM
port, greater pixel-draw rates are achieved by the device’s
(8 × 8) × 2 block-write feature. The block-write mode allows 16
bits of data (present in an on-chip color-data register) to be
written to any combination of eight adjacent column-address
locations. As many as 128 bits of data can be written to memory
during each CAS\ cycle time. Also, on the DRAM port and
SAM port, a write mask or a write-per-bit feature allows
masking of any combination of the 16 inputs/outputs on any
write cycle. The persistent write-per-bit feature uses a mask
register that, once loaded, can be used on subsequent write
cycles without reloading. The SMJ55161A also offers byte
control which can be applied in read cycles, write cycles, block-
write cycles, load-write-mask-register cycles, and load-color-
register cycles. The SMJ55161A also offers extended-data-
output (EDO) mode. The EDO mode is effective in both the
page-mode and standard DRAM cycles.
The SMJ55161A offers a split-register-transfer read
(DRAM-to-SAM) feature for the serial register (SAM port) that
enables real-time-register-load implementation for continuous
serial-data streams without critical timing requirements. The
register is divided into a high half and a low half. While one half
is being read out of the SAM port, the other half can be loaded
from the memory array. For applications not requiring real-time
register load (for example, loads done during CRT-retrace
periods), the full-register mode of operation is retained to
simplify system design.
The SAM port is designed for maximum performance. Data
can be accessed from the SAM at serial rates up to 50 MHz.
During the split-register-transfer read operations, internal
circuitry detects when the last bit position is accessed from the
active half of the register and immediately transfers control to
the opposite half. A separate output, QSF, is included to
indicate which half of the serial register is active.
All inputs, outputs, and clock signals on the SMJ55161 are
compatible with Series 54/74 TTL. All address lines and data-in
lines are latched on-chip to simplify system design. All data-
out lines are unlatched to allow greater system flexibility.
The SMJ55161A is offered in a 68-pin ceramic pin-grid-
array package (GB suffix) and a 64-pin ceramic flatpack (HKC
suffix).
The SMJ55161A is supported by a broad line of graphic
processors and control devices from Texas Instruments. See
Table 2 and Table 4 for additional information.
Additional features of the 55161A include MASKED
FLASH WRITE which allows for data in color register to be
written into all the memory locations of a selected row.
SM55161A
Production
SMJ55161A
Rev. 1.6 03/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
VRAM
Austin Semiconductor, Inc.
TABLE 1: DRAM & SAM FUNCTIONS
RAS\ FALL
FUNCTION
CASx\
Reserved (do not use)
CBR refresh (no reset) and stop-
point set
4
6
2
SM55161A
Production
DQ0-DQ15
1
3
CASx\
FALL
DSF
L
H
L
H
L
H
L
DSF
X
X
X
X
X
X
L
ADDRESS
RAS\
X
Stop
point
X
X
Row
Address
Row
Address
5
TRG\
L
X
X
X
L
L
H
WE\
L
L
H
H
H
H
L
CASX\
X
X
X
X
Tap
Point
Tap
Point
RAS\
X
X
X
X
X
X
L
L
L
L
H
H
H
MNE
CASL\
CODE
CASU\
WE\
X
---
X
X
X
X
X
Valid
Data
CBRS
CBR
CBRN
RT
SRT
RWM
CBR refresh (option reset)
CBR refresh (no reset)
7
Full-register-transfer read
Split-register-transfer read
DRAM write
(nonpersistent write-per-bit)
DRAM block write
(nonpersistent write-per-bit)
DRAM write
(persistent write-per-bit)
DRAM block write
(persistent write-per-bit)
DRAM write (nonmasked)
Row
Column Write
Address Address Mask
H
H
L
L
H
Block
Row
Write Column
Address
BWM
Address
Mask Mask
A3-A8
Row
Column
Address Address
Block
Row
Address
Address
A3-A8
Row
Column
Address Address
Block
Row
Address
Address
A3-A8
Refresh
Address
Refresh
Address
Row
Address
Row
Address
Row
Address
X
X
Tap
Point
Tap
Point
X
X
Valid
Data
RWM
H
H
L
L
L
H
H
L
L
H
X
Column
BWM
Mask
Valid
Data
Column
Mask
Write
Mask
Color
Data
X
X
---
RW
H
H
H
L
L
X
DRAM block write (nonmasked)
8
H
H
H
L
H
X
BW
Load write-mask register
Load color register
Masked Write Transfer
9
H
H
H
9
H
H
L
L
H
H
H
L
L
L
H
H
L
H
H
L
H
X
X
X
X
X
Write
Mask
Write
Mask
Write
Mask
LMR
LCR
MWT
MSWT
FWM
Masked Split Write Transfer
H
9
Masked Flash Write Transfer
H
LEGEND:
Col Mask = H: Write to address/column enabled
Write Mask = H: Write to I/O enabled
X = Don’t Care
NOTES:
1. DQ0–DQ15 are latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later.
2. Logic L is selected when either or both CASL\ and CASU\ are low.
3. The column address and block address are latched on the first falling edge of CASx\.
4. CBRS cycle should be performed immediately after the power-up initialization cycle.
5. A0–A3, A8: don’t care; A4–A7: stop-point code
6. CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
7. CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option
reset) cycle.
9. MWT, MSWT, FWM function shown are for nonpersistent mask writes. These functions also support persistent mask write.
SMJ55161A
Rev. 1.6 03/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
NXP MCU
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