Dual USB Port Power Supply Controller
ISL6185
The ISL6185 USB power controller family provides fully
independent overcurrent (OC) fault protection for two or more
USB ports.
This product family consists of sixteen individual functional
product variants and three package options. It is operation
rated for a nominal +2.5V to +5V range and is specified over the
full commercial and industrial temperature ranges.
Each ISL6185 type incorporates in a single package two 71mΩ
P-channel MOSFET power switches for power control. Each
features internal current monitoring, accurate current limiting,
and current limited delay to turn-off, for system supply
protection along with control and communication I/O.
The ISL6185 family offers product variants with specified
continuous output current levels of 0.6A, 1.1A, 1.5A or 1.8A; enable
active high or low inputs; and latch off or automatic retry after
overcurrent turn-off, making these devices well suited for many
low-power applications.
This family of ICs is offered in an industry-standard SOIC pinout
and also in the 70% smaller 3x3 DFN packages providing similar
or enhanced performance in the smallest possible package.
Features
• 2.5V to 5V Operating Range
• 71mΩ Integrated Power P-channel MOSFET Switches
• Continuous Current Options for 0.6A, 1.1A, 1.5A and 1.8A
• Thermally Insensitive 12ms of Current Limiting Prior to
Turn-Off
• Output Discharges with Reverse Current Blocking When
Disabled
• Latch-off or Auto Restart Options
• 1µA Off-State Supply Current
• Enable Polarity Options
• Industry-standard Pin for Pin SOIC, and Smaller DFN Packages
Available
• UL Recognized, File Number: E333469
Applications
• USB 1, 2, 3 Port Power Management
• Low Power (18W) Electronic Circuit Limiting and Breaker
D+
D-
U
S
B
C
O
N
T
R
O
L
L
E
R
USB
PORT 1
VBUS
1.3
1.2
1.1
1.0
0.9
0.8
0.7
ENABLE_1
FAULT_1
+5V
VIN
OUT_1
GND
ISL6185
FAULT_2
ENABLE_2
OUT_2
VBUS
USB
PORT_2
D+
D-
USB PORT POWER
NORMALIZED r
DS(ON)
-40
-25
0
25
45
75
TEMPERATURE (°C)
85
115
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. NORMALIZED r
DS(ON)
TEMPERATURE
CHARACTERISTIC CURVE
March 8, 2012
FN6937.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2010, 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6185
Ordering Information
(Continued)
PART
NUMBER
(Notes 1, 2, 3)
ISL61852FIRZ
ISL61852GIRZ
ISL61852HIRZ
ISL61852IIRZ
ISL61852JIRZ
ISL61852KIRZ
ISL61852LIRZ
ISL61853AIRZ
ISL61853BIRZ
ISL61853CIRZ
ISL61853DIRZ
ISL61853EIRZ
ISL61853FIRZ
ISL61853GIRZ
ISL61853HIRZ
ISL61853IIRZ
ISL61853JIRZ
ISL61853KIRZ
ISL61853LIRZ
ISL61853MIRZ
ISL61853NIRZ
ISL61853OIRZ
ISL61853PIRZ
ISL61851EVAL1Z
ISL61852EVAL1Z
ISL61853EVAL1Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information pages for
ISL6185XXC
(commercial version) and
ISL6185XXI
(industrial version).
For more information on MSL please see techbrief
TB363.
PART MARKING
52FI
52GI
52HI
52II
52JI
52KI
52LI
53AI
53BI
53CI
53DI
53EI
53FI
53GI
53HI
53II
53JI
53KI
53LI
53MI
53NI
53OI
53PI
EN/EN
INPUT
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
V
IN
= 5V
MAXIMUM
CONTINUOUS IOUT
(A)
0.6
1.1
1.1
1.5
1.5
1.5
1.5
0.6
0.6
1.1
1.1
0.6
0.6
1.1
1.1
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
LATCH/AUTO
RETRY
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
TEMP.
RANGE (°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-free)
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
PKG.
DWG. #
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
8 Lead SOIC Evaluation Platform with ISL61851A installed
8 Lead DFN Evaluation Platform with ISL61852H installed
10 Lead DFN Evaluation Platform with ISL61853I installed
4
FN6937.3
March 8, 2012
ISL6185
Pin Configurations
ISL6185
(8 LD SOIC/DFN)
TOP VIEW
GND
VIN
EN1/EN1
EN2/EN2
1
2
3
4
(GND)
EPAD
DFN Only
8
7
6
5
FLT1
OUT1
OUT2
FLT2
GND
VIN
VIN
EN1/EN1
EN2/EN2
1
2
3
4
5
(GND)
EPAD
ISL6185
(10 LD DFN)
TOP VIEW
10
9
8
7
6
FLT1
OUT1
NC
OUT2
FLT2
Pin Descriptions
PIN NUMBER
8 Ld
SOIC/DFN
1
2
10 Ld DFN
1
2, 3
SYMBOL
GND
VIN
IC ground reference.
DESCRIPTION
Chip bias, Controlled Voltage Input, Undervoltage Lock Out (UVLO). VIN provides chip bias voltage. At
VIN < 1.7V chip functionality is disabled, FLT is active and floating, and OUT is held low. Range 0V to
5.5V.
Enable/Disable inputs, Active high (EN) and active low (EN) options enable the power switch. These
inputs have internal 1MΩ pull-off resistors. Range 0V to VIN.
Overcurrent Fault Indicator. FLT floats and is disabled until VIN >V
UVLO
. This output is pulled low after
the current limit time-out period has expired. Fault is not signaled due to over-temperature shut down.
Range 0V to VIN.
Controlled Supply Output. Upon an OC condition, I
OUT
is current limited. Current limit response time is
within 200µs. This output remains in current limit for a nominal 12ms before being turned off either for
the latch or auto retry versions. Range 0V to VIN.
This pin is not electrically connected internally.
Thermal Dissipation Exposed PAD Range: Connect to GND.
3,
4
5,
8
4,
5
6,
10
EN1, EN1/
EN2, EN2
FLT2
FLT1
6,
7
7,
9
OUT2,
OUT1
-
PD
(DFN only)
8
PD
NC
EPAD
5
FN6937.3
March 8, 2012
FPGA/CPLD
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