ISD5008
Single-Chip Voice Record/Playback Device
4-, 5-, 6-, and 8-Minute Durations
Preliminary Datasheet
ISD5008 PRODUCT SUMMARY
The ISD5008 ChipCorder product is a fully-inte-
grated, single-chip solution which provides seam-
less integration of enhanced voice record and
playback features for digital cellular phones (GSM,
CDMA, TDMA, PDC, and PHS), automotive com-
munications, GPS/navigation systems, and porta-
ble communication products. This low-power, 3-
volt product enables customers to quickly and
easily integrate 4 to 8 minutes of voice storage
features such as one-way and two-way (full du-
plex) call record, voice memo record, and call
screening/answering machine functionality.
Like other ChipCorder products, the ISD5008 inte-
grates the sampling clock, anti-aliasing and
smoothing filters, and the multi-level storage array
on a single-chip. For enhanced voice features,
the ISD5008 eliminates external circuitry by also in-
tegrating automatic gain control (AGC), a power
amplifier/speaker driver, volume control, sum-
ming amplifiers, analog switches, and a car kit in-
terface. Input level adjustable amplifiers are also
included, providing a flexible interface for multiple
applications.
Figure: ISD5008 Block Diagram
FTHRU
6dB
INP
FILTO
CHIP SET
ANA
OUT
AMP
1
ANA OUT MUX
ANA OUT+
ANA OUT-
MICROPHONE
MIC+
MIC -
AGCCAP
AUX IN
1.0/1.414/2.0/2.828
MIC IN
INP
SUM1 MUX
AGC
(AGPD)
1
Σ
2
SUM1
Summing
AMP
SUM1
ARRAY
1
SUM1
Input Source MUX
Low Pass
Filter
1
FILTO
ANA IN
2
Σ
)
SUM2
Summing
AMP
VOL
SUM2
Filter
Filter
MUX
(AOPD)
3
FILTO
ANA IN
ARRAY
(
S1M0
)
S1M1
(FLS0)
(FLPD)
CAR KIT
AUX IN
(
Internal
Clock
2
S2M0
S2M1
AUX IN
AMP
(INS0)
1
1
( )
AOS0
AOS1
AOS2
SUM1 MUX
(AXPD)
2
(
AXG0
AXG1
2
)
(
S1S0
)
S1S1
Multilevel
Storage Array
FILTO
CAR KIT
AUX
OUT
AMP
XCLK
0.625/0.883/1.25/1.76
(
FLD0
)
FLD1
AUX OUT
Output MUX
VOL
SUM2
SPEAKER
Spkr.
AMP
CHIP SET
ANA IN
SP+
SP-
ANA IN
AMP
(AIPD)
1
ANA IN
2
SUM1
INP
ANA IN
SUM2
Volume
Control
3
(
1
OPS0
OPS1
)
2
Vol MUX
(
OPA0
)
OPA1
2
(
AIG0
)
AIG1
Power Conditioning
2
( )
VOL0
VOL1
VOL2
(VLPD)
(
VLS0
)
VLS1
Device Control
V
CCA
V
SSA
V
SSA
V
SSA
V
SSD
V
SSD
V
CCD
V
CCD
SCLK SS MOSI MISO INT
RAC
August 2000
ISD · 2727 North First Street, San Jose, CA 95134 · TEL: 408/943-6666 · FAX: 408/544-1787 · http://www.isd.com
ISD5008 Product
Duration/sample rate selection is accomplished
via software, allowing customers to optimize qual-
ity and duration for various features within the
same end product.
The ISD5008 device is designed for use in a micro-
processor- or microcontroller-based system. Ad-
dress, control, and duration selection are
accomplished through a Serial Peripheral Inter-
face (SPI) or Microwire Serial Interface to minimize
pin count.
Recordings are stored in on-chip nonvolatile
memory cells, providing zero-power message
storage. This unique, single-chip solution is made
possible through ISD’s patented multilevel storage
technology. Voice and audio signals are stored
directly into solid-state memory in their natural, un-
compressed form, providing superior quality voice
and music reproduction.
ENHANCED VOICE FEATURES
•
•
•
•
•
•
•
One or two-way (full duplex) conversation
record (record signal summation)
One- or two-way (full duplex) message
playback (while on a call)
Voice memo record and playback
Private call screening
In-terminal answering machine
Personalized outgoing message (given caller
ID information from host chip set)
Private call announce while on call (given
CIDCW information from host chip set)
EASY-TO-USE AND CONTROL
•
•
No compression algorithm development
required
User-controllable sample rates of 8.0 kHz,
6.4 kHz, 5.3 kHz, or 4.0 kHz providing up to
8 minutes of voice storage.
Microcontroller SPI or Microwire™ Serial
Interface
Fully addressable to handle multiple
messages in 1200 rows
ISD5008 FEATURES
FULLY-INTEGRATED SOLUTION
•
•
•
Single-chip voice record/playback solution
Integrated sampling clock, anti-aliasing and
smoothing filters, and multi-level storage array
Integrated analog features such as automatic
gain control (AGC), audio gating switches,
speaker driver (23mW with 8 ohm load),
summing amplifiers, volume control, and an
AUX IN/AUX OUT interface (e.g., for car kits).
•
•
HIGH QUALITY SOLUTION
•
•
•
High quality voice and music reproduction
ISD’s standard 100-year message retention
(typical)
100,000 record cycles (typical)
LOW-POWER CONSUMPTION
•
•
Single +3 volt supply
Operating current:
I
CC Play
= 15 mA (typical)
I
CC Rec
= 25 mA (typical)
I
CC Feedthru
= 12 mA (typical)
Standby current:
I
SB
= 1 µA
OPTIONS
•
•
Available in die form, PDIP, SOIC, TSOP, and
chip scale packaging (CSP)
Compact µBGA chip scale package
available for portable applications
Extended temperature (-20 to +70°C) and
industrial temperature (-40 to +85°C) versions
available
•
•
•
•
Power consumption controlled by SPI or
Microwire control register
Most stages can be individually powered
down for minimum power consumption
ii
Voice Solutions in Silicon
™
Table of Contents
1
DETAILED DESCRIPTION ................................................. .................... 1
1.1
Speech/Sound Quality ...................................... .................... 1
1.2
Duration ............................................................ .................... 1
1.3
Flash Storage .................................................... .................... 1
1.4
Microcontroller Interface ....................................................... 1
1.5
Programming .................................................... .................... 1
PIN DESCRIPTIONS ........................................................ .................... 2
2.1
Digital I/O Pins ................................................... .................... 2
2.2
Analog I/O Pins .................................................. .................... 3
2.3
Power and Ground Pins .................................... .................... 6
INTERNAL FUNCTIONAL BLOCKS .................................... .................... 7
SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION .......... .................... 13
4.1
Message Cueing .............................................. .................... 13
4.2
Power-Up Sequence ......................................... .................... 14
4.3
SPI Port .............................................................. .................... 15
4.4
SPI Control Register ........................................... .................... 15
OPERATIONAL MODES DESCRIPTION ............................. .................... 21
5.1
Feed Through Mode ......................................... .................... 21
5.2
Call Record ...................................................... .................... 23
5.3
Memo Record .................................................. .................... 24
5.4
Memo and Call Record Playback .................... .................... 24
TIMING DIAGRAMS ....................................................... .................... 34
DEVICE PHYSICAL DIMENSIONS ..................................... .................... 36
ORDERING INFORMATION ........................................... .................... 42
2
3
4
5
6
7
8
ISD5008 Product
1
1.1
DETAILED DESCRIPTION
SPEECH/SOUND QUALITY
1.3
FLASH STORAGE
The ISD5008 ChipCorder product can be config-
ured via software to operate at 4.0, 5.3, 6.4, and
8.0 kHz sampling frequencies, allowing the user a
choice of speech quality options. Increasing the
duration decreases the sampling frequency and
bandwidth, which affects sound quality. Table 1
compares filter pass band and product durations.
The speech samples are stored directly into on-chip
nonvolatile memory without the digitization and
compression associated with other solutions. Di-
rect analog storage provides a natural sounding
reproduction of voice, music, tones, and sound
effects not available with most solid-state solu-
tions.
One of the benefits of ISD’s ChipCorder technology
is the use of on-chip nonvolatile memory, which pro-
vides zero-power message storage. The message
is retained for up to 100 years (typically) without
power. In addition, the device can be re-record-
ed over 100,000 times (typically).
1.4
MICROCONTROLLER INTERFACE
1.2
DURATION
A four-wire (SCLK, MOSI, MISO, SS) SPI interface is
provided for ISD5008 control, addressing func-
tions, and sample rate selection. The ISD5008 is
configured to operate as a peripheral slave de-
vice with a microcontroller-based SPI bus inter-
face. Read/Write access to all the internal registers
occurs through this SPI interface. An interrupt sig-
nal (INT) and internal read-only Status Register are
provided for handshake purposes.
To meet end system requirements, the ISD5008
device is a single-chip solution which provides
from 4 to 8 minutes of voice record and playback,
depending on the sample rates defined by cus-
tomer software.
1.5
PROGRAMMING
Table 1:
Input Sample
Rate (kHz)
8.0
6.4
5.3
4.0
Input Sample Rate to Duration
Duration Typical Filter Pass Band
(Minutes)
(kHz)
4.0
5.0
6.0
8.0
3.4
2.7
2.3
1.7
The ISD5008 series is also ideal for playback-only
applications, where single or multiple message
Playback is controlled through the SPI port. Once
the desired message configuration is created, du-
plicates can easily be generated via an ISD or
third-party programmers. For more information on
available application tools and programmers
please see the ISD web site at www.isd.com.
ISD
1
ISD5008 Product
2
2.1
SCLK
PIN DESCRIPTIONS
DIGITAL I/O PINS
(Serial Clock)
OVF Flag
. The overflow flag indicates that the end
of the ISD5008’s analog memory has been
reached during a record or playback operation.
EOM Flag.
The end of message flag is set only
during playback, when an EOM is found. There are
eight possible EOM markers per row.
The SCLK is the clock input to the ISD5008. Gener-
ated by the master microcontroller, the SCLK syn-
chronizes data transfers in and out of the device
through the MISO and MOSI lines. Data is latched
into the ISD5008 on the rising edge of SCLK and
shifted out on the falling edge.
RAC
(Row Address Clock)
SS
(Slave Select)
RAC is an open drain output pin that marks the
end of a row. At the 8 kHz sample frequency, the
duration of this period is 200 ms. There are 1,200
rows of memory in the ISD5008 devices. RAC stays
HIGH for 175 ms and stays LOW for the remaining
25 ms before it reaches the end of the row.
The RAC pin remains HIGH for 109.38 µsec and
stays LOW for 15.63 µsec under the Message Cue-
ing mode. See Table 15 Timing Parameters for
RAC timing information at other sample rates.
When a record command is first initiated, the RAC
pin remains HIGH for an extra T
RACLO
period, to
load sample and hold circuits internal to the de-
vice. The RAC pin can be used for message man-
agement techniques.
This input, when LOW, will select the ISD5008 de-
vice.
MOSI
(Master Out Slave In)
MOSI is the serial data input to the ISD5008 de-
vice. The master microcontroller places data to
be clocked into the ISD5008 device on the MOSI
line one-half cycle before the rising edge of SCLK.
Data is clocked into the device LSB (Least Signifi-
cant Bit) first.
XCLK
MISO
(Master In Slave Out)
MISO is the serial data output of the ISD5008 de-
vice. Data is clocked out on the falling edge of
SCLK. This output goes into a high-impedance
state when the device is not selected. Data is
clocked out of the device LSB first.
(External Clock Input)
The external clock input for the ISD5008 product
has an internal pull-down device. Normally, the
ISD5008 is operated at one of four internal rates
selected for its internal oscillator by the Sample
Rate Select bits. If greater precision is required, the
device can be clocked through the XCLK pin as
described in Table 2.
Because the antialiasing and smoothing filters
track the Sample Rate Select bits, one must, for
optimum performance, change the external
clock
AND
the Sample Rate Configuration bits to
one of the four values to properly set the filters to
the correct cutoff frequency as described in Table
3. The duty cycle on the input clock is not critical,
as the clock is immediately divided by two inter-
nally. If the XCLK is not used, this input should be
connected to V
SSD
.
INT
(Interrupt)
INT is an open drain output pin. The ISD5008 inter-
rupt pin goes LOW and stays LOW when an Over-
flow (OVF) or End of Message (EOM) marker is
detected. Each operation that ends in an EOM or
OVF generates an interrupt, including the mes-
sage cueing cycles. The interrupt is cleared the
next time an SPI cycle is completed. The interrupt
status can be read by a RINT instruction that will
give one of the two flags out the MISO line.
2
Voice Solutions in Silicon
™
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