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74ALVCH162244MTD

产品描述Bus Driver, ALVC/VCX/A Series, 4-Func, 4-Bit, True Output, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48
产品类别逻辑    逻辑   
文件大小68KB,共6页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
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74ALVCH162244MTD概述

Bus Driver, ALVC/VCX/A Series, 4-Func, 4-Bit, True Output, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48

74ALVCH162244MTD规格参数

参数名称属性值
厂商名称Fairchild
零件包装代码TSSOP
包装说明TSSOP,
针数48
Reach Compliance Codeunknown
系列ALVC/VCX/A
JESD-30 代码R-PDSO-G48
长度12.5 mm
逻辑集成电路类型BUS DRIVER
位数4
功能数量4
端口数量2
端子数量48
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE WITH SERIES RESISTOR
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd)7.6 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)1.65 V
标称供电电压 (Vsup)1.8 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
宽度6.1 mm

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74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26Ω Series Resistor in Outputs
September 2001
Revised September 2001
74ALVCH162244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
and 26
Series Resistor in Outputs
General Description
The ALVCH162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ALVCH162244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level
The 74ALVCH162244 is also designed with 26
series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVCH162244 is designed for low voltage (1.65V to
3.6V) V
CC
applications with output capability up to 3.6V.
The 74ALVCH162244 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
s
1.65V–3.6V V
CC
supply operation
s
3.6V tolerant control inputs and outputs
s
Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s
26
series resistors in outputs
s
t
PD
4.2 ns max for 3.0V to 3.6V V
CC
4.9 ns max for 2.3V to 2.7V V
CC
7.6 ns max for 1.65V to 1.95V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Ordering Code:
Order Number
74ALVCH162244MTD
Package
Number
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Input (Active LOW)
Bushold Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation
DS500632
www.fairchildsemi.com

 
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