Not Recommended for New Design,
Replace with CAT24C16
CAT24WC01/02/04/08/16
1K/2K/4K/8K/16K-Bit Serial EEPROM
FEATURES
s
400 kHz I
2
C Bus Compatible*
s
1.8 to 5.5Volt Operation
s
Low Power CMOS Technology
s
Write Protect Feature
s
Self-Timed Write Cycle with Auto-Clear
s
1,000,000 Program/Erase Cycles
s
100 Year Data Retention
s
8-pin DIP, SOIC, TSSOP and MSOP packages
- "Green" package option available
s
Commercial, Industrial, Automotive and
— Entire Array Protected When WP at V
IH
s
Page Write Buffer
Extended Temperature Ranges
DESCRIPTION
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K-
bit Serial CMOS EEPROM internally organized as 128/
256/512/1024/2048 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces de-
vice power requirements. The the CAT24WC01/02/04/
08/16 feature a 16-byte page write buffer. The device
operates via the I
2
C bus serial interface, has a special
write protection feature, and is available in 8-pin DIP,
SOIC, TSSOP and MSOP packages.
PIN CONFIGURATION
DIP Package (P, L, GL)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
BLOCK DIAGRAM
SOIC Package (J, W, GW)
EXTERNAL LOAD
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
5020 FHD F01
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
TSSOP Package (U, Y, GY)
MSOP Package (R, Z, GZ)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
(MSOP and TSSOP available for CAT24WC01,
CAT24WC02 and CAT24WC04 only)
SDA
VCC
WP
SCL
SDA WP
START/STOP
LOGIC
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
XDEC
CONTROL
LOGIC
E
2
PROM
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
Function
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
+1.8V to +5.5V Power Supply
Ground
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
HIGH VOLTAGE/
TIMING CONTROL
DATA IN STORAGE
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1022, Rev. N
CAT24WC01/02/04/08/16
Not Recommended
for New Design,
Replace with CAT24C01
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
Max.
Units
Cycles/Byte
Years
Volts
mA
1,000,000
100
2000
100
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Limits
Symbol
I
CC
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0V)
Output Low Voltage (V
CC
= 1.8V)
–1
V
CC
x 0.7
Min.
Typ.
Max.
3
1
10
10
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
Units
mA
µA
µA
µA
V
V
V
V
I
OL
= 3 mA
I
OL
= 1.5 mA
Test Conditions
f
SCL
= 100 KHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(3)
C
IN(3)
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL, WP)
Max.
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1022, Rev. N
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Not Recommended for New Design,
Replace with CAT24C01
A.C. CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
CAT24WC01/02/04/08/16
Read & Write Cycle Limits
CAT24WCXX-1.8
1.8V-5.5V
Symbol
F
SCL
T
I
(1)
CAT24WCXX
2.5V-5.5V
Min.
Max.
100
200
3.5
4.7
4
4.7
4
4.7
0
50
1.2
0.6
1.2
0.6
0.6
0
50
1
300
4
100
0.6
100
0.3
300
4.5V-5.5V
Min.
Max.
400
200
1
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Parameter
Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs
SCL Low to SDA Data Out and ACK
Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Min.
Max.
100
200
3.5
t
AA
t
BUF
(1)
4.7
4
4.7
4
4.7
0
50
1
30 0
4
100
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Power-Up Timing(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
Write Cycle Limits
Symbol
t
WR
Parameter
Write Cycle Time
Min.
Typ.
Max
10
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1022, Rev. N
CAT24WC01/02/04/08/16
Not Recommended
for New Design,
Replace with CAT24C01
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT24WC01/02/04/08/16 serial clock input pin is
used to clock all data transfers into or out of the device.
This is an input pin.
SDA:
Serial Data/Address
The CAT24WC01/02/04/08/16 bidirectional serial data/
address pin is used to transfer data into and out of the
device. The SDA pin is an open drain output and can be
wire-ORed with other open drain or open collector
outputs.
A0, A1, A2:
Device Address Inputs
These inputs set device address when cascading mul-
tiple devices. When these pins are left floating the
default values are zeros.
A maximum of eight devices can be cascaded when
FUNCTIONAL DESCRIPTION
The CAT24WC01/02/04/08/16 supports the I
2
C Bus
data transmission protocol. This Inter-Integrated Circuit
Bus protocol defines any device that sends data to the
bus to be a transmitter and any device receiving data to
be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START
and STOP conditions for bus access. The CAT24WC01/
02/04/08/16 operates as a Slave device. Both the Mas-
ter and Slave devices can operate as either transmitter
or receiver, but the Master device controls which mode
is activated. A maximum of 8 devices (CAT24WC01 and
CAT24WC02), 4 devices (CAT24WC04), 2 devices
(CAT24WC08) and 1 device (CAT24WC16) may be
connected to the bus as determined by the device
address inputs A0, A1, and A2.
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHIGH
tLOW
tR
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
SDA OUT
5020 FHD F03
tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
5020 FHD F05
START BIT
Doc. No. 1022, Rev. N
STOP BIT
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Not Recommended for New Design,
Replace with CAT24C01
using either CAT24WC01 or CAT24WC02 device. All
three address pins are used for these densities. If only
one CAT24WC01 or CAT24WC02 is addressed on the
bus, all three address pins (A0, A1and A2) can be left
floating or connected to V
SS
.
A total of four devices can be addressed on a single bus
when using CAT24WC04 device. Only A1 and A2
address pins are used with this device. The A0 address
pin is a no connect pin and can be tied to V
SS
or left
floating. If only one CAT24WC04 is being addressed on
the bus, the address pins (A1 and A2) can be left floating
or connected to V
SS
.
Only two devices can be cascaded when using
CAT24WC08. The only address pin used with this
device is A2. The A0 and A1 address pins are no
connect pins and can be tied to V
SS
or left floating. If only
one CAT24WC08 is being addressed on the bus, the
address pin (A2) can be left floating or connected to V
SS
.
The CAT24WC16 is a stand alone device. In this case,
all address pins (A0, A1and A2) are no connect pins and
can be tied to V
SS
or left floating.
WP:
Write Protect
If the WP pin is tied to V
CC
the entire memory array
becomes Write Protected (READ only). When the WP
pin is tied to V
SS
or left floating normal read/write
operations are allowed to the device.
CAT24WC01/02/04/08/16
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC01/02/04/08/16
monitor the SDA and SCL lines and will not respond until
this condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24WC01/02/04/08/16 (see Fig. 5).
The next three significant bits (A2, A1, A0) are the device
address bits and define which device or which part of the
device the Master is accessing. Up to eight CAT24WC01/
02, four CAT24WC04, two CAT24WC08, and one
CAT24WC16 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC01/02/04/08/16 monitors
the bus and responds with an acknowledge (on the SDA
line) when its address matches the transmitted slave
I
2
C Bus Protocol
The following defines the features of the I
2
C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1022, Rev. N
FPGA/CPLD
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