Philips Semiconductors
Product specification
Triple 3-input AND gate
FEATURES
•
Wide supply voltage range from1.2 to 3.6 V
•
Inputs accept voltages up to 5.5 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Output capability: standard
•
I
CC
category: SSI
•
In accordance with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
74LVC11D
74LVC11DB
74LVC11PW
74LVC11BQ
TEMPERATURE RANGE
PINS
−40
to +85
°C
−40
to +85
°C
−40
to +85
°C
−40
to +85
°C
14
14
14
14
PACKAGE
SO14
SSOP14
TSSOP14
DHVQFN14
MATERIAL
plastic
plastic
plastic
plastic
PARAMETER
propagation delay nA, nB, nC to nY
input capacitance
power dissipation capacitance per gate
notes 1 and 2
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
TYPICAL
3.7
5.0
26
DESCRIPTION
74LVC11
The 74LVC11 is a high-performance, low power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74LVC11 provides the 3-input AND function.
UNIT
ns
pF
pF
CODE
SOT108-1
SOT337-1
SOT402-1
SOT762-1
2004 Jan 13
2
Philips Semiconductors
Product specification
Triple 3-input AND gate
74LVC11
handbook, halfpage
handbook, halfpage
1A
1
VCC
14
13
12
1C
1Y
3C
3B
3A
1A
1B
2A
2B
2C
2Y
GND
1
2
3
4
5
6
7
MNA791
14 VCC
13 1C
12 1Y
1B
2A
2B
2C
2Y
2
3
4
5
6
7
Top view
GND
8
3Y
11
11 3C
10 3B
9
3A
GND
(1)
11
10
9
8 3Y
MNA970
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO14 and (T)SSOP14.
Fig.2 Pin configuration DHVQFN14.
handbook, halfpage
1
2
13
3
4
5
9
10
11
1A
1B
1C
2A
2B
2C
3A
3B
3C
MNA793
handbook, halfpage
1
2
&
12
13
3
1Y
12
2Y
6
4
5
&
6
3Y
8
9
10
11
MNA792
&
8
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2004 Jan 13
4
MEMS传感器
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