74LV08
Quad 2-input AND gate
Rev. 03 — 6 April 2009
Product data sheet
1. General description
The 74LV08 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC08 and 74HCT08.
The 74LV08 provides a quad 2-input AND function.
2. Features
I
I
I
I
I
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
°C
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV08N
74LV08D
74LV08DB
74LV08PW
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP14
SO14
SSOP14
TSSOP14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
Type number
NXP Semiconductors
74LV08
Quad 2-input AND gate
4. Functional diagram
1
2
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
4
2Y
6
5
&
6
A
Y
&
8
B
mna221
&
3
3Y
8
9
10
4Y
11
12
&
mna222
11
13
mna223
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
74LV08
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
001aaj959
14 V
CC
13 4B
1A
12 4A
11 4Y
10 3B
9
8
3A
3Y
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
74LV08
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
001aaj960
Fig 4.
Pin configuration DIP14, SO14
Fig 5.
Pin configuration (T)SSOP14
74LV08_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 6 April 2009
2 of 13
NXP Semiconductors
74LV08
Quad 2-input AND gate
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
V
CC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
X
H
[1]
Function selection
[1]
Output
nB
X
L
H
nY
L
L
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
−40 °C
to +125
°C
DIP14 package
SO14, SSOP14, TSSOP14
[1]
[2]
[2]
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Min
−0.5
-
-
-
-
−50
−65
-
-
Max
+7.0
±20
±50
±25
50
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For DIP14 packages: above 70
°C
the value of P
tot
derates linearly with 12 mW/K.
For SO14 packages: above 70
°C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60
°C
the value of P
tot
derates linearly with 5.5 mW/K.
74LV08_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 6 April 2009
3 of 13
NXP Semiconductors
74LV08
Quad 2-input AND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Parameter
supply voltage
[1]
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
[1]
Conditions
Min
1.0
0
0
−40
-
-
-
-
Typ
3.3
-
-
+25
-
-
-
-
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
°C
ns/V
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−100 µA;
V
CC
= 1.2 V
I
O
=
−100 µA;
V
CC
= 2.0 V
I
O
=
−100 µA;
V
CC
= 2.7 V
I
O
=
−100 µA;
V
CC
= 3.0 V
I
O
=
−100 µA;
V
CC
= 4.5 V
I
O
=
−6
mA; V
CC
= 3.0 V
I
O
=
−12
mA; V
CC
= 4.5 V
-
1.8
2.5
2.8
4.3
2.4
3.6
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
1.8
2.5
2.8
4.3
2.2
3.5
-
-
-
-
-
-
-
V
V
V
V
V
V
V
−40 °C
to +85
°C
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
0.3V
CC
−40 °C
to +125
°C
Unit
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
0.3V
CC
V
V
V
V
V
V
V
V
74LV08_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 6 April 2009
4 of 13
NXP Semiconductors
74LV08
Quad 2-input AND gate
Table 6.
Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
OL
LOW-level output voltage
Conditions
V
I
= V
IH
or V
IL
I
O
= 100
µA;
V
CC
= 1.2 V
I
O
= 100
µA;
V
CC
= 2.0 V
I
O
= 100
µA;
V
CC
= 2.7 V
I
O
= 100
µA;
V
CC
= 3.0 V
I
O
= 100
µA;
V
CC
= 4.5 V
I
O
= 6 mA; V
CC
= 3.0 V
I
O
= 12 mA; V
CC
= 4.5 V
I
I
I
CC
∆I
CC
C
I
[1]
−40 °C
to +85
°C
Min
-
-
-
-
-
-
-
-
-
-
-
Typ
[1]
0
0
0
0
0
0.25
0.35
-
-
-
3.5
Max
-
0.2
0.2
0.2
0.2
0.40
0.55
1.0
20.0
500
-
−40 °C
to +125
°C
Unit
Min
-
-
-
-
-
-
-
-
-
-
-
Max
-
0.2
0.2
0.2
0.2
0.50
0.65
1.0
40
850
-
V
V
V
V
V
V
V
µA
µA
µA
pF
input leakage current
supply current
additional supply current
input capacitance
V
I
= V
CC
or GND; V
CC
= 5.5 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
per input; V
I
= V
CC
−
0.6 V;
V
CC
= 2.7 V to 3.6 V
Typical values are measured at T
amb
= 25
°C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see
Figure 7.
Symbol Parameter
t
pd
propagation delay
Conditions
nA, nB to nY; see
Figure 6
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V; C
L
= 15 pF
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
C
PD
power dissipation
capacitance
C
L
= 50 pF; f
i
= 1 MHz;
V
I
= GND to V
CC
[4]
[3]
[3]
[2]
−40 °C
to +85
°C
Min
-
-
-
-
-
-
-
Typ
[1]
45
15
11
7
9.0
-
10
Max
-
26
17
-
15
11
-
−40 °C
to +125
°C
Min
-
-
-
-
-
-
-
Max
-
33
21
-
19
14
-
Unit
ns
ns
ns
ns
ns
ns
pF
[1]
[2]
[3]
[4]
All typical values are measured at T
amb
= 25
°C.
t
pd
is the same as t
PLH
and t
PHL
.
Typical values are measured at nominal supply voltage (V
CC
= 3.3 V).
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz, f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
74LV08_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 6 April 2009
5 of 13
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