74HC21
Dual 4-input AND gate
Rev. 7 — 30 November 2015
Product data sheet
1. General description
The 74HC21 is a dual 4-input AND gate. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C.
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC21D
74HC21DB
74HC21PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO14
SSOP14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
Type number
NXP Semiconductors
74HC21
Dual 4-input AND gate
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC Logic symbol
Fig 4.
Logic diagram
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SOT108-1
Fig 6.
Pin configuration SOT337-1 and SOT402-1
74HC21
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 30 November 2015
2 of 14
NXP Semiconductors
74HC21
Dual 4-input AND gate
5.2 Pin description
Table 2.
Symbol
1A, 1B, 1C, 1D
n.c.
1Y
GND
2Y
2A, 2B, 2C, 2D
V
CC
Pin description
Pin
1, 2, 4, 5
3, 11
6
7
8
9, 10, 12, 13
14
Description
data input
not connected
data output
ground (0 V)
data output
data input
supply voltage
6. Functional description
Table 3.
Input
nA
L
X
X
X
H
[1]
Function table
[1]
Output
nB
X
L
X
X
H
nC
X
X
L
X
H
nD
X
X
X
L
H
nY
L
L
L
L
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
Max
+7
20
20
25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
SO14 and (T)SSOP14 packages
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
74HC21
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 30 November 2015
3 of 14
NXP Semiconductors
74HC21
Dual 4-input AND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
V
I
V
O
t/V
Parameter
supply voltage
input voltage
output voltage
input transition rise and fall
rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
T
amb
ambient temperature
Conditions
Min
2.0
0
0
-
-
-
40
Typ
5.0
-
-
-
1.67
-
-
Max
6.0
V
CC
V
CC
625
139
83
+125
Unit
V
V
V
ns/V
ns/V
ns/V
C
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
Min
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
input leakage
current
supply current
input
capacitance
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
3.5
0.1
0.1
0.1
0.26
0.26
0.1
2.0
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1
20
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
40
-
V
V
V
V
V
A
A
pF
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
25
C
Typ
1.2
2.4
3.2
0.8
2.1
2.8
Max
-
-
-
0.5
1.35
1.8
40 C
to +85
C 40 C
to +125
C
Unit
Min
1.5
3.15
4.2
-
-
-
Max
-
-
-
0.5
1.35
1.8
Min
1.5
3.15
4.2
-
-
-
Max
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
74HC21
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 30 November 2015
4 of 14
NXP Semiconductors
74HC21
Dual 4-input AND gate
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; test circuit see
Figure 8.
Symbol Parameter
t
pd
propagation
delay
Conditions
Min
nA, nB, nC or nD to nY;
see
Figure 7
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
CC
= 5.0 V; C
L
= 15 pF
t
t
transition time
nY output; see
Figure 7
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
C
PD
power
dissipation
capacitance
V
I
= GND to V
CC
[3]
[2]
[1]
25
C
Typ
Max
40 C
to +85
C
Min
Max
40 C
to +125
C
Unit
Min
Max
-
-
-
-
-
-
-
-
33
12
10
10
19
7
6
15
110
22
19
-
75
15
13
-
-
-
-
-
-
-
-
-
140
28
24
-
95
19
16
-
-
-
-
-
-
-
-
-
165
33
28
-
110
22
19
-
ns
ns
ns
ns
ns
ns
ns
pF
[1]
[2]
[3]
t
pd
is the same as t
PHL
and t
PLH
.
t
t
is the same as t
THL
and t
TLH
.
C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC2
f
i
N +
(C
L
V
CC2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC2
f
o
) = sum of outputs.
74HC21
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 30 November 2015
5 of 14
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