74ALVC08
Quad 2-input AND gate
Rev. 3 — 5 October 2017
Product data sheet
1
General description
The 74ALVC08 is a high-performance, low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall
times.
The 74ALVC08 provides the 2-input AND function.
2
Features and benefits
•
•
•
•
•
•
•
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
–
JESD8-7 (1.65 V to 1.95 V)
–
JESD8-5 (2.3 V to 2.7 V)
–
JESD8B/JESD36 (2.7 V to 3.6 V)
•
ESD protection:
–
HBM JESD22-A114E exceeds 2000 V
–
MM JESD22-A115-A exceeds 200 V
3
Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74ALVC08D
-40 °C to +85 °C
SO14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
74ALVC08PW -40 °C to +85 °C
74ALVC08BQ -40 °C to +85 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Nexperia
Quad 2-input AND gate
74ALVC08
4
Functional diagram
1
2
&
3
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
4
1Y
2Y
3Y
4Y
mna222
3
6
8
11
&
5
6
9
10
&
8
A
12
13
&
11
B
Y
mna221
mna223
Figure 1. Logic symbol
Figure 2. IEC logic symbol
Figure 3. Logic diagram (one gate)
5
Pinning information
5.1 Pinning
74ALVC08
terminal 1
index area
1B
1Y
2A
2
3
4
5
6
7
GND
3Y
8
GND
(1)
14 V
CC
1A
1
13 4B
12 4A
11 4Y
10 3B
9
3A
74ALVC08
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
aaa-27559
2B
2Y
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
74ALVC08
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
aaa-027560
aaa-027561
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
Transparent top view
(1) This is not a supply pin, the
substrate is attached to this pad using
conductive die attach material. There is
no electrical or mechanical requirement
to solder this pad however if it is
soldered the solder land should remain
floating or be connected to GND.
Figure 4. Pin configuration SO14
Figure 6. Pin configuration
Figure 5. Pin configuration TSSOP14 DHVQFN14
74ALVC08
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 5 October 2017
2 / 14
Nexperia
Quad 2-input AND gate
74ALVC08
5.2 Pin description
Table 2. Pin description
Symbol
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
V
CC
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6
Functional description
[1]
Table 3. Function table
Input
nA
L
L
H
H
Output
nB
L
H
L
H
nY
L
L
L
H
[1] H = HIGH voltage level; L = LOW voltage level
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
= -40 °C to +85 °C
[3]
[1]
Conditions
Min
-0.5
-0.5
-0.5
-0.5
-
-
-
-
-100
-65
-
Max
+4.6
+4.6
+4.6
-50
±50
±50
100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
°C
mW
none
power-down mode, V
CC
= 0 V
V
I
< 0 V
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
[1] [2]
[2]
V
CC
+ 0.5 V
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When V
CC
= 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
[3] For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
74ALVC08
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 5 October 2017
3 / 14
Nexperia
Quad 2-input AND gate
74ALVC08
8
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 1.65 to 3.6 V
power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
-40
0
0
Max
3.6
3.6
V
CC
3.6
+85
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
Table 5. Recommended operating conditions
Symbol
V
CC
V
I
V
O
T
amb
Δt/ΔV
9
Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol
V
IH
Parameter
HIGH-level
input voltage
Conditions
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level
input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
= -100 μA; V
CC
= 1.65 V to 3.6 V
I
O
= -6 mA; V
CC
= 1.65 V
I
O
= -12 mA; V
CC
= 2.3 V
I
O
= -18 mA; V
CC
= 2.3 V
I
O
= -12 mA; V
CC
= 2.7 V
I
O
= -18 mA; V
CC
= 3.0 V
I
O
= -24 mA; V
CC
= 3.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 100 μA; V
CC
= 1.65 V to 3.6 V
I
O
= 6 mA; V
CC
= 1.65 V
I
O
= 12 mA; V
CC
= 2.3 V
I
O
= 18 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 18 mA; V
CC
= 3.0 V
I
O
= 24 mA; V
CC
= 3.0 V
74ALVC08
All information provided in this document is subject to legal disclaimers.
T
amb
= -40 °C to +85 °C
Min
0.65 × V
CC
1.7
2.0
-
-
-
V
CC
- 0.2
1.25
1.8
1.7
2.2
2.4
2.2
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
1.51
2.10
2.01
2.53
2.76
2.68
-
0.11
0.17
0.25
0.16
0.23
0.30
[1]
Unit
-
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Max
0.35 × V
CC
V
0.7
0.8
-
-
-
-
-
-
-
0.2
0.3
0.4
0.6
0.4
0.4
0.55
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 5 October 2017
4 / 14
Nexperia
Quad 2-input AND gate
Symbol
I
I
I
OFF
I
CC
ΔI
CC
C
I
Parameter
input leakage current
power-off
leakage current
supply current
additional
supply current
input capacitance
Conditions
V
CC
= 3.6 V; V
I
= 3.6 V or GND
V
CC
= 0 V; V
I
or V
O
= 3.6 V
V
CC
= 3.6 V; V
I
= V
CC
or GND; I
O
= 0 A
per input pin; V
CC
= 3.0 V to 3.6 V;
V
I
= V
CC
- 0.6 V; I
O
= 0 A
-
-
-
-
-
T
amb
= -40 °C to +85 °C
Min
Typ
[1]
74ALVC08
Unit
μA
μA
μA
μA
pF
Max
±5
±10
20
750
-
±0.1
±0.1
0.2
5
3.5
[1] All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25 °C.
10 Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit, see
Figure 8.
Symbol
t
pd
Parameter
propagation delay
Conditions
nA, nB to nY; see
Figure 7
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
C
PD
power dissipation
capacitance
per gate; V
I
= GND to V
CC
; V
CC
= 3.3 V
[3]
[2]
T
amb
= -40 °C to +85 °C
Min
1.2
1.0
-
1.2
-
Typ
[1]
Unit
Max
5.3
3.2
3.0
2.9
-
ns
ns
ns
ns
pF
2.7
1.9
2.2
2.0
24
[1] Typical values are measured at T
amb
= 25 °C and V
CC
= 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively
[2] t
pd
is the same as t
PHL
and t
PLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in μW).
2
2
P
D
= C
PD
× V
CC
× f
i
× N + Σ(C
L
× V
CC
× f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
2
Σ(C
L
× V
CC
× f
o
) = sum of the outputs
74ALVC08
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 5 October 2017
5 / 14
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
