74HC109-Q100; 74HCT109-Q100
Dual JK flip-flop with set and reset; positive-edge-trigger
Rev. 1 — 28 September 2016
Product data sheet
1. General description
The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop
featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD)
inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active
LOW inputs and operate independently of the clock input. The nJ and nK inputs control
the state changes of the flip-flops as described in the mode select function table. The nJ
and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation. The JK design allows operation as a D-type flip-flop by
connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use
of current limiting resistors to interface inputs to voltages in excess of V
CC
.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Input levels:
For 74HC109-Q100: CMOS level
For 74HCT109-Q100: TTL level
J and K inputs for easy D-type flip-flop
Toggle flip-flop or “do nothing” mode
Specified in compliance with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
NXP Semiconductors
74HC109-Q100; 74HCT109-Q100
Dual JK flip-flop with set and reset; positive-edge-trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC109D-Q100
74HCT109D-Q100
40 C
to +125
C
Name Description
SO16
Version
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Type number
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one flip-flop)
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
2 of 17
NXP Semiconductors
74HC109-Q100; 74HCT109-Q100
Dual JK flip-flop with set and reset; positive-edge-trigger
5. Pinning information
5.1 Pinning
Fig 4.
Pin configuration for SO16
5.2 Pin description
Table 2.
Symbol
1RD, 2RD
1J, 2J
1K, 2K
1CP, 2CP
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
V
CC
Pin description
Pin
1, 15
2, 14
3, 13
4, 12
5, 11
6, 10
7, 9
8
16
Description
asynchronous reset input (active LOW)
synchronous input
synchronous input
clock input (LOW-to-HIGH; edge-triggered)
asynchronous set input (active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
supply voltage
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
3 of 17
NXP Semiconductors
74HC109-Q100; 74HCT109-Q100
Dual JK flip-flop with set and reset; positive-edge-trigger
6. Functional description
Table 3.
Function selection
[1]
Input
nSD
Asynchronous set
Asynchronous reset
Undetermined
Toggle
Load 0 (reset)
Load 1 (set)
Hold no change
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time before the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time before the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time before the LOW-to-HIGH CP transition
X = don’t care
= LOW-to-HIGH CP transition
Operating modes
Output
nRD
H
L
L
H
H
H
H
nCP
X
X
X
nJ
X
X
X
h
l
h
l
nK
X
X
X
l
l
h
h
nQ
H
L
H
q
L
H
q
nQ
L
H
H
q
H
L
q
L
H
L
H
H
H
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
50
65
Max
+7
20
20
25
+50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
SO16 package
[1]
-
For SO16 package: above 70
C,
the value of P
tot
derates linearly with 8 mW/K.
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
4 of 17
NXP Semiconductors
74HC109-Q100; 74HCT109-Q100
Dual JK flip-flop with set and reset; positive-edge-trigger
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC109-Q100
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT109-Q100
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC109-Q100
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
input leakage
current
supply current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
0.1
0.1
0.1
0.26
0.26
0.1
4.0
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1
40
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
80
V
V
V
V
V
A
A
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
5 of 17
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