74HC109; 74HCT109
Rev. 4 — 1 April 2020
Dual JK flip-flop with set and reset; positive-edge-trigger
Product data sheet
1. General description
The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual nJ and
nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and
nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently
of the clock input. The nJ and nK inputs control the state changes of the flip-flops as described
in the mode select function table. The nJ and nK inputs must be stable one set-up time prior
to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation
as a D-type flip-flop by connecting the nJ and nK inputs together. Inputs include clamp diodes.
It enables the use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall
times.
2. Features and benefits
•
Input levels:
•
For 74HC109: CMOS level
•
For 74HCT109: TTL level
J and K inputs for easy D-type flip-flop
Toggle flip-flop or "do nothing" mode
Specified in compliance with JEDEC standard no. 7A
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC109D
74HCT109D
74HC109DB
74HCT109DB
74HCT109PW
-40 °C to +125 °C
TSSOP16
-40 °C to +125 °C
SSOP16
-40 °C to +125 °C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
Nexperia
74HC109; 74HCT109
Dual JK flip-flop with set and reset; positive-edge-trigger
4. Functional diagram
5 11
1SD 2SD
2
14
4
12
3
13
SD
1Q
1J
Q
J
2J
2Q
1CP
CP
2CP
FF
1Q
1K
Q
K
2Q
2K
RD
1RD 2RD
1 15
mna858
6
10
7
9
5
2
4
3
1
S
1J
C1
1K
R
(a)
6
7
11
14
12
13
15
S
1J
C1
1K
R
(b)
mna856
10
9
Fig. 1.
Logic symbol
Fig. 2.
IEC logic symbol
Q
K
C
C
C
C
Q
J
C
C
C
C
S
R
C
C
aaa-024066
CP
Fig. 3.
Logic diagram (one flip-flop)
74HC_HCT109
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 4 — 1 April 2020
2 / 17
Nexperia
74HC109; 74HCT109
Dual JK flip-flop with set and reset; positive-edge-trigger
5. Pinning information
5.1. Pinning
74HC109
74HCT109
1RD
1J
1K
1CP
1SD
1Q
1Q
GND
1
2
3
4
5
6
7
8
aaa-024067
16 V
CC
15 2RD
14 2J
13 2K
12 2CP
11 2SD
10 2Q
9
2Q
1RD
1J
1K
1CP
1SD
1Q
1Q
GND
1
2
3
4
5
6
7
8
74HC109
74HCT109
16 V
CC
15 2RD
14 2J
13 2K
12 2CP
11 2SD
10 2Q
9
aaa-024068
2Q
Fig. 4.
Pin configuration for SOT109-1 (SO16)
Fig. 5.
Pin configuration for SOT338-1 (SSOP16) and
SOT403-1 (TSSOP16)
5.2. Pin description
Table 2. Pin description
Symbol
1RD, 2RD
1J, 2J
1K, 2K
1CP, 2CP
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
V
CC
Pin
1, 15
2, 14
3, 13
4, 12
5, 11
6, 10
7, 9
8
16
Description
asynchronous reset input (active LOW)
synchronous input
synchronous input
clock input (LOW-to-HIGH; edge-triggered)
asynchronous set input (active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
supply voltage
74HC_HCT109
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 4 — 1 April 2020
3 / 17
Nexperia
74HC109; 74HCT109
Dual JK flip-flop with set and reset; positive-edge-trigger
6. Functional description
Table 3. Function selection
H = HIGH voltage level; h = HIGH voltage level one set-up time before the LOW-to-HIGH CP transition;
L = LOW voltage level; l = LOW voltage level one set-up time before the LOW-to-HIGH CP transition;
q = lower case letters indicate the state of the referenced output one set-up time before the LOW-to-HIGH CP transition;
X = don’t care; ↑ = LOW-to-HIGH CP transition
Operating modes
Asynchronous set
Asynchronous reset
Undetermined
Toggle
Load 0 (reset)
Load 1 (set)
Hold no change
Input
nSD
L
H
L
H
H
H
H
nRD
H
L
L
H
H
H
H
nCP
X
X
X
↑
↑
↑
↑
nJ
X
X
X
h
l
h
l
nK
X
X
X
l
l
h
h
Output
nQ
H
L
H
q
L
H
q
nQ
L
H
H
q
H
L
q
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
-0.5 V < V
O
< V
CC
+ 0.5 V
Min
-0.5
-
-
-
-
-50
-65
[1]
-
Max
+7
±20
±20
±25
+50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
For SOT109-1 (SO16) package: P
tot
derates linearly with 12.4 mW/K above 110 °C.
For SOT338-1 (SSOP16) package: P
tot
derates linearly with 8.5 mW/K above 91 °C.
For SOT403-1 (TSSOP16) package: P
tot
derates linearly with 8.5 mW/K above 91 °C.
74HC_HCT109
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 4 — 1 April 2020
4 / 17
Nexperia
74HC109; 74HCT109
Dual JK flip-flop with set and reset; positive-edge-trigger
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
-40
-
-
-
74HC109
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Min
4.5
0
0
-40
-
-
-
74HCT109
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
°C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
74HC109
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
= -20 μA; V
CC
= 2.0 V
I
O
= -20 μA; V
CC
= 4.5 V
I
O
= -20 μA; V
CC
= 6.0 V
I
O
= -4.0 mA; V
CC
= 4.5 V
I
O
= -5.2 mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20 μA; V
CC
= 2.0 V
I
O
= 20 μA; V
CC
= 4.5 V
I
O
= 20 μA; V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
input leakage
current
supply current
input
capacitance
V
I
= V
CC
or GND; V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
3.5
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
±1
40
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
80
-
V
V
V
V
V
μA
μA
pF
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
25 °C
Typ
Max
-40 °C to
+85 °C
Min
Max
-40 °C to
+125 °C
Min
Max
Unit
74HC_HCT109
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 4 — 1 April 2020
5 / 17
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