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74HC109; 74HCT109
Dual JK flip-flop with set and reset; positive-edge-trigger
Rev. 3 — 1 August 2016
Product data sheet
1. General description
The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual
nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and
complementary nQ and nQ outputs. The set and reset are asynchronous active LOW
inputs and operate independently of the clock input. The nJ and nK inputs control the state
changes of the flip-flops as described in the mode select function table. The nJ and nK
inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for
predictable operation. The JK design allows operation as a D-type flip-flop by connecting
the nJ and nK inputs together. Inputs include clamp diodes. It enables the use of current
limiting resistors to interface inputs to voltages in excess of V
CC
.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features and benefits
Input levels:
For 74HC109: CMOS level
For 74HCT109: TTL level
J and K inputs for easy D-type flip-flop
Toggle flip-flop or “do nothing” mode
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74HC109; 74HCT109
Dual JK flip-flop with set and reset; positive-edge-trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC109D
74HCT109D
74HC109DB
74HCT109DB
74HCT109PW
40 C
to +125
C
40 C
to +125
C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
SOT403-1
40 C
to +125
C
Name
SO16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Type number
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one flip-flop)
74HC_HCT109
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 1 August 2016
2 of 19
NXP Semiconductors
74HC109; 74HCT109
Dual JK flip-flop with set and reset; positive-edge-trigger
5. Pinning information
5.1 Pinning
Fig 4.
Pin configuration for SO16
Fig 5.
Pin configuration for (T)SSOP16
5.2 Pin description
Table 2.
Symbol
1RD, 2RD
1J, 2J
1K, 2K
1CP, 2CP
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
V
CC
Pin description
Pin
1, 15
2, 14
3, 13
4, 12
5, 11
6, 10
7, 9
8
16
Description
asynchronous reset input (active LOW)
synchronous input
synchronous input
clock input (LOW-to-HIGH; edge-triggered)
asynchronous set input (active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
supply voltage
74HC_HCT109
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 1 August 2016
3 of 19
NXP Semiconductors
74HC109; 74HCT109
Dual JK flip-flop with set and reset; positive-edge-trigger
6. Functional description
Table 3.
Function selection
[1]
Input
nSD
Asynchronous set
Asynchronous reset
Undetermined
Toggle
Load 0 (reset)
Load 1 (set)
Hold no change
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time before the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time before the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time before the LOW-to-HIGH CP transition
X = don’t care
= LOW-to-HIGH CP transition
Operating modes
Output
nRD
H
L
L
H
H
H
H
nCP
X
X
X
nJ
X
X
X
h
l
h
l
nK
X
X
X
l
l
h
h
nQ
H
L
H
q
L
H
q
nQ
L
H
H
q
H
L
q
L
H
L
H
H
H
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
50
65
Max
+7
20
20
25
+50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
SO16 and (T)SSOP16 packages
[1]
-
For SO16 packages: above 70
C,
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60
C,
the value of P
tot
derates linearly with 5.5 mW/K.
74HC_HCT109
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 1 August 2016
4 of 19
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