74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge
trigger
Rev. 8 — 23 January 2013
Product data sheet
1. General description
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type
flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and
complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs
and operate independently of the clock input. Information on the data input is transferred
to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be
stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP1G74DC
74AUP1G74GT
74AUP1G74GF
74AUP1G74GD
74AUP1G74GM
74AUP1G74GN
74AUP1G74GS
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
VSSOP8
XSON8
XSON8
XSON8
XQFN8
XSON8
XSON8
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1
1.95
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1
0.5 mm
SOT1089
Type number
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3
2
0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6
1.6
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2
1.0
0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1.0
0.35 mm
SOT902-2
SOT1116
SOT1203
4. Marking
Table 2.
Marking codes
Marking code
[1]
p74
p74
54
p74
p74
54
54
Type number
74AUP1G74DC
74AUP1G74GT
74AUP1G74GF
74AUP1G74GD
74AUP1G74GM
74AUP1G74GN
74AUP1G74GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
SD
D
CP
SD
D
CP
FF
Q
RD
RD
001aah725
Q
Q
S
Q
C1
1D
R
001aah726
Fig 1.
74AUP1G74
Logic symbol
Fig 2.
IEC logic symbol
© NXP B.V. 2013. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 8 — 23 January 2013
2 of 28
NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Q
C
C
C
D
C
Q
C
RD
C
SD
001aae087
CP
C
C
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
74AUP1G74
CP
1
8
V
CC
D
2
7
SD
74AUP1G74
Q
CP
D
Q
GND
1
2
3
4
001aae322
3
6
RD
8
7
6
5
V
CC
SD
RD
Q
GND
4
5
Q
001aae323
Transparent top view
Fig 4.
Pin configuration SOT765-1
Fig 5.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74AUP1G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 23 January 2013
3 of 28
NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
74AUP1G74
terminal 1
index area
SD
1
V
CC
8
74AUP1G74
CP
D
Q
GND
1
2
3
4
8
7
6
5
V
CC
7
CP
RD
SD
RD
Q
Q
2
6
D
3
4
5
Q
GND
001aae324
001aai217
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT996-2
Fig 7.
Pin configuration SOT902-2
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
CP
D
Q
GND
Q
RD
SD
V
CC
1
2
3
4
5
6
7
8
SOT902-2
7
6
5
4
3
2
1
8
clock input
data input
complement output
ground (0 V)
true output
asynchronous reset input (active LOW)
asynchronous set input (active LOW)
supply voltage
Description
7. Functional description
Table 4.
Input
SD
L
H
L
[1]
Function table for asynchronous operation
[1]
Output
RD
H
L
L
CP
X
X
X
D
X
X
X
Q
H
L
H
Q
L
H
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
74AUP1G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 23 January 2013
4 of 28
NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 5.
Input
SD
H
H
[1]
Function table for synchronous operation
[1]
Output
RD
H
H
CP
D
L
H
Q
n+1
L
H
Q
n+1
H
L
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH CP transition;
Q
n+1
= state after the next LOW-to-HIGH CP transition.
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
[1]
Max
+4.6
-
+4.6
-
+4.6
20
+50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
0.5
-
-
50
65
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For VSSOP8 packages: above 110
C
the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
0.8
0
0
0
40
-
Max
3.6
3.6
V
CC
3.6
+125
200
Unit
V
V
V
V
C
ns/V
74AUP1G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 23 January 2013
5 of 28
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