74LVC74A-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 2 — 5 April 2013
Product data sheet
1. General description
The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop. It has individual data (nD)
inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ
outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the nQ output on the
LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
5 V tolerant inputs for interlacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74LVC74A-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC74AD-Q100
40 C
to +125
C
SO14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
74LVC74APW-Q100
40 C
to +125
C
74LVC74ABQ-Q100
40 C
to +125
C
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
1SD
SD
D
CP
FF
Q
4 10
1SD 2SD
2
12
3
11
1D
D
2D
1CP
CP
2CP
SD
Q
1Q
2Q
5
9
4
3
2
1
S
C1
1D
R
12
S
C1
1D
R
mna419
4
2
3
1D
1CP
Q
1Q
5
1Q
6
RD
5
1
6
10
1RD
2SD
SD
D
CP
FF
8
RD
13
2RD
mna420
2D
2CP
FF
Q
10
1Q
2Q
6
8
11
12
13
mna418
Q
2Q
9
9
11
RD
1RD 2RD
1 13
Q
2Q
8
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Functional diagram
74LVC74A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 5 April 2013
2 of 18
NXP Semiconductors
74LVC74A-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
Q
C
C
C
C
D
C
RD
C
C
Q
C
SD
mna421
CP
C
C
Fig 4.
Logic diagram for one flip-flop
5. Pinning information
5.1 Pinning
/9&$4
5'
'
&3
6'
4
4
*1'
DDD
/9&$4
5'
*1'
4
*1'
9
&&
5'
'
&3
6'
4
4
WHUPLQDO
LQGH[ DUHD
'
&3
6'
4
4
9
&&
5'
'
&3
6'
4
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration for SO14 and TSSOP14
Fig 6.
Pin configuration for DHVQFN14
74LVC74A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 5 April 2013
3 of 18
NXP Semiconductors
74LVC74A-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
5.2 Pin description
Table 2.
Symbol
1RD, 2RD
1D, 2D
1CP, 2CP
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
V
CC
Pin description
Pin
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true output
complement output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nSD
L
H
L
[1]
Function table
[1]
Output
nRD
H
L
L
nCP
X
X
X
nD
X
X
X
nQ
H
L
H
nQ
L
H
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care
Table 4.
Input
nSD
H
H
[1]
Function table
[1]
Output
nRD
H
H
nCP
nD
L
H
nQ
n+1
L
H
nQ
n+1
H
L
H = HIGH voltage level; L = LOW voltage level;
= LOW-to-HIGH transition; Q
n+1
= state after the next LOW-to-HIGH CP transition;
X = don’t care
74LVC74A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 5 April 2013
4 of 18
NXP Semiconductors
74LVC74A-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO14 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For TSSOP14 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
C
the value of P
tot
derates linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and
fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
Conditions
for maximum speed performance
for low-voltage applications
Min
1.65
1.2
0
0
40
0
0
Typ
-
-
-
-
-
-
-
Max
3.6
3.6
5.5
V
CC
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
74LVC74A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 5 April 2013
5 of 18
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