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74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 7 — 20 November 2012
Product data sheet
1. General description
The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs,
clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the nQ output on the
LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features and benefits
5 V tolerant inputs for interlacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC74AD
74LVC74ADB
40 C
to +125
C
40 C
to +125
C
Name
SO14
SSOP14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
Type number
74LVC74APW
40 C
to +125
C
74LVC74ABQ
40 C
to +125
C
DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1
quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
1SD
SD
D
CP
FF
Q
4 10
1SD 2SD
2
12
3
11
1D
D
2D
1CP
CP
2CP
SD
Q
1Q
2Q
5
9
4
3
2
1
S
C1
1D
R
12
S
C1
1D
R
mna419
4
2
3
1D
1CP
Q
1Q
5
1Q
6
RD
5
1
6
10
1RD
2SD
SD
D
CP
FF
8
RD
13
2RD
mna420
2D
2CP
FF
Q
10
1Q
2Q
6
8
11
12
13
mna418
Q
2Q
9
9
11
RD
1RD 2RD
1 13
Q
2Q
8
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Functional diagram
74LVC74A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 20 November 2012
2 of 19
NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Q
C
C
C
C
D
C
RD
C
C
Q
C
SD
mna421
CP
C
C
Fig 4.
Logic diagram for one flip-flop
5. Pinning information
5.1 Pinning
1RD
2
3
4
5
6
7
GND
2Q
8
1
1D
1CP
1SD
1Q
1Q
GND
2
3
4
5
6
7
001aad106
1RD
1
14 V
CC
13 2RD
12 2D
terminal 1
index area
1D
1CP
1SD
1Q
14 V
CC
13 2RD
12 2D
11 2CP
10 2SD
9
2Q
74
11 2CP
10 2SD
74
GND
(1)
1Q
9
8
2Q
2Q
001aad107
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration for SO14 and (T)SSOP14
Fig 6.
Pin configuration for DHVQFN14
74LVC74A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 20 November 2012
3 of 19
NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
5.2 Pin description
Table 2.
Symbol
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true output
complement output
ground (0 V)
complement output
true output
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
asynchronous reset-direct input (active LOW)
supply voltage
6. Functional description
Table 3.
Input
nSD
L
H
L
[1]
Function table
[1]
Output
nRD
H
L
L
nCP
X
X
X
nD
X
X
X
nQ
H
L
H
nQ
L
H
H
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Table 4.
Input
nSD
H
H
[1]
Function table
[1]
Output
nRD
H
H
nCP
nD
L
H
nQ
n+1
L
H
nQ
n+1
H
L
H = HIGH voltage level
L = LOW voltage level
= LOW-to-HIGH transition
Q
n+1
= state after the next LOW-to-HIGH CP transition
X = don’t care
74LVC74A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 20 November 2012
4 of 19
FPGA/CPLD
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