Hardware Design Guide, Revision 1
May 26, 2006
TMXF28155
Supermapper
™
155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
1 Introduction
The last issue of this data sheet was October 13, 2003. A change history can be found in
Section 9, Change History, on
page 63.
Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to
the text are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Formatting
or grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or tables will be specifically
mentioned.
This document is based on the June 2002
Supermapper
data sheet with some clarifications. The documentation package
for the TMXF28155
Supermapper
155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0 system chip consists of the follow-
ing documents:
The
Supermapper Family Register Description
and the
Supermapper Family System Design Guide.
These two docu-
ments are available on a password-protected website.
The
Supermapper Product Description,
and the
Supermapper Hardware Design Guide
(this document). These two doc-
uments are available on the public website shown below.
To access related documents, including the documents mentioned above, please go to the following public website, or con-
tact your Agere representative (see the last page of this document).
http://www.agere.com/enterprise_metro_access/mappers_muxes.html
This document describes the hardware interfaces to the Agere Systems Inc. TMXF28155
Supermapper
device. Information
relevant to the use of the device in a board design is covered. Pin descriptions, dc electrical characteristics, timing
diagrams, ac timing parameters, packaging, and operating conditions are included.
Telecom Bus
(to 2 additional
Supermappers)
DS3 PLL IF
30
2
DS2
AIS Clk
TCB & TDL
RCB & RDL
1
10
High Speed IF
4
CDR
M13
MUX
TMUX
STS3/
STM1/
STS1/
AU-3
SPEMPR
STS1/AU3/AU4
FRM
x28/x21
DS1/J1/E1
8
PLL Interface
155.52 Mbits/s STS-3/STM-1
51.84 Mbits/s STS-1/AU-3
System Interfaces
6
(x1) DS3
Clock/Sync
6
XC
x28/x21
VT/TU
VTMPR
DS1/J1/E1
DS2
DS3
Multifunction System I/O
148
Switching Modes:
8PSB
- x672 DS0/E0
4CHI
- x672 DS0/E0
Transport Modes:
8
4DS1/J1/E1
(X29) - x28/x21 + prot.
4DS2
- x7 + prot.
MSP 1 + 1
155.52 Mbits/s STS-3/STM-1
51.84 Mbits/s STS-1/AU-3
TPG/TPM
NSMI Modes:
MPU
Interface & Control
6
6
6
47
x28/x21
DS1/E1
DJA
2
4DS1/J1/E1
x28/x21
4DS3
- x1
4STS1
- x1
TOAC
LOPOH
POAC
DS1 & E1
XClks
EHB 10/17/03 Supermapper
MPU IF
Figure 1-1.
Supermapper
Block Diagram and High-Level Interface Definition
TMXF28155
Supermapper
155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
Hardware Design Guide, Revision 1
May 26, 2006
Table of Contents
Contents
Page
1 Introduction ........................................................................................................................................................................1
2 Pin Information ...................................................................................................................................................................6
2.1 456-Pin PBGA Pin Diagram ........................................................................................................................................6
2.2 Pin Assignments for 456-Pin PBGA by Pin Number Order .........................................................................................7
2.3 Pin Assignments for 456-Pin PBGA by Signal Name ................................................................................................10
2.4 Pin Descriptions .........................................................................................................................................................13
2.4.1 High-Speed I/O Pin Descriptions .....................................................................................................................13
2.4.2 Protection Switch I/O Pin Description ..............................................................................................................14
2.4.3 Telecom Bus (Low-Speed I/O) Pin Description ................................................................................................14
2.4.4 TOAC and POAC .............................................................................................................................................17
2.4.5 Miscellaneous Signals ......................................................................................................................................18
2.4.6 DS3 Port ...........................................................................................................................................................18
2.4.7 Low-Order Path Overhead Access Channel ....................................................................................................21
2.4.8 Framer PLL ......................................................................................................................................................25
2.4.9 Test Pins ..........................................................................................................................................................28
3 Pin Assignment Matrix .....................................................................................................................................................30
4 Electrical Characteristics .................................................................................................................................................33
4.1 Absolute Maximum Ratings .......................................................................................................................................33
4.2 Thermal Parameters (Definitions and Values) ...........................................................................................................33
4.3 Reliability ...................................................................................................................................................................34
4.4 Handling Precautions ................................................................................................................................................35
4.5 Operating Conditions .................................................................................................................................................35
4.5.1 Power Consumption .........................................................................................................................................35
4.6 Logic Interface Characteristics ..................................................................................................................................36
4.7 LVDS Interface Characteristics .................................................................................................................................37
5 Timing Characteristics .....................................................................................................................................................38
5.1 TMUX Block Timing ...................................................................................................................................................38
5.2 DS3 Timing ................................................................................................................................................................42
5.3 M13 Timing ................................................................................................................................................................43
5.4 VT Mapper Timing .....................................................................................................................................................44
5.4.1 VT Mapper Lower-Order Path Overhead Interface Timing ..............................................................................44
5.5 Concentration Highway (CHI) Timing ........................................................................................................................45
5.6 Parallel System Bus Timing .......................................................................................................................................46
5.7 NSMI Timing (6-Pin) (to/from Framer) .......................................................................................................................47
5.8 NSMI Timing (7-Pin) (to/from Framer) .......................................................................................................................47
5.9 CHI Interface Timing ..................................................................................................................................................48
5.10 PSB Interface Timing ...............................................................................................................................................49
5.11 Framer DS1/E1 Interface Timing .............................................................................................................................50
5.12 DJA DS1/E1 Interface Timing ..................................................................................................................................51
5.13 M13 DS1/E1 Interface Timing .................................................................................................................................52
5.14 Microprocessor Interface Timing .............................................................................................................................53
5.14.1 Synchronous Mode ........................................................................................................................................53
5.14.2 Asynchronous Mode ......................................................................................................................................55
5.15 General-Purpose Interface Timing ..........................................................................................................................58
6 Telecom Bus Operation ...................................................................................................................................................59
6.1 Introduction ................................................................................................................................................................59
6.2 Telecom Bus Pin Descriptions ...................................................................................................................................59
6.3 Telecom Bus Timing Diagrams .................................................................................................................................60
7 Ordering Information ........................................................................................................................................................61
8 Outline Diagram ...............................................................................................................................................................62
8.1 456-Pin PBGA ...........................................................................................................................................................62
9 Change History ................................................................................................................................................................63
9.1 Navigating Through an Adobe Acrobat ® Document ................................................................................................63
2
Agere Systems Inc.
Hardware Design Guide, Revision 1
May 26, 2006
TMXF28155
Supermapper
155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
Table of Contents
(continued)
Tables
Page
Table 2-1. Pin/Name...............................................................................................................................................................7
Table 2-2. Pin Assignments for 456-Pin PBGA by Signal Name..........................................................................................10
Table 2-3. High-Speed I/O Pin Descriptions.........................................................................................................................13
Table 2-4. Protection Switch I/O Pin Description..................................................................................................................14
Table 2-5. Telecom Bus (Low-Speed I/O) Pin Description...................................................................................................15
Table 2-6. TOAC and POAC ................................................................................................................................................17
Table 2-7. Miscellaneous Signals.........................................................................................................................................18
Table 2-8. DS3 Port..............................................................................................................................................................19
Table 2-9. DS3 Port C-Bit and Datalink Access ...................................................................................................................19
Table 2-10. M13 Multiplexer/Demultiplexer Receive Section ...............................................................................................20
Table 2-11. Reference Clocks ..............................................................................................................................................20
Table 2-12. Low-Order Path Overhead Access Channel .....................................................................................................21
Table 2-13. Multifunction System Interface ..........................................................................................................................22
Table 2-14. Framer PLL .......................................................................................................................................................25
Table 2-15. Microprocessor Interfaces .................................................................................................................................26
Table 2-16. General-Purpose Interface ................................................................................................................................27
Table 2-17. Test Pins ...........................................................................................................................................................28
Table 2-18. LVDS Control Pins ............................................................................................................................................29
Table 2-19. Analog Power and Ground Signals ...................................................................................................................29
Table 3-1. Pin Matrix ............................................................................................................................................................30
Table 4-1. Absolute Maximum Ratings.................................................................................................................................33
Table 4-2. Thermal Parameter Values .................................................................................................................................34
Table 4-3. Reliability Data ....................................................................................................................................................34
Table 4-4. Handling Precaution ............................................................................................................................................35
Table 4-5. Recommended Operating Conditions .................................................................................................................35
Table 4-6. Power Consumption ............................................................................................................................................35
Table 4-7. Logic Interface Characteristics ............................................................................................................................36
Table 4-8. LVDS Interface Characteristics ...........................................................................................................................37
Table 5-1. High-Speed Input Clock Specifications ...............................................................................................................38
Table 5-2. Output Clock Specifications ................................................................................................................................39
Table 5-3. Input Timing Specifications .................................................................................................................................40
Table 5-4. Output Timing Specifications...............................................................................................................................41
Table 5-5. DS3 Input Clock Specifications ...........................................................................................................................42
Table 5-6. Input Timing Specifications .................................................................................................................................42
Table 5-7. Output Timing Specifications...............................................................................................................................42
Table 5-8. M13 Clock Specifications ....................................................................................................................................43
Table 5-9. Input Timing Specifications .................................................................................................................................43
Table 5-10. Output Timing Specifications.............................................................................................................................43
Table 5-11. VT Mapper Receive Path Overhead Detailed Timing .......................................................................................44
Table 5-12. CHI Transmit Timing Characteristics.................................................................................................................45
Table 5-13. CHI Receive Timing Characteristics..................................................................................................................45
Table 5-14. PSB Interface Transmit Timing Characteristics.................................................................................................46
Table 5-15. PSB Interface Receive Timing Characteristics..................................................................................................46
Table 5-16. NSMI Input/Output Clock Specifications ...........................................................................................................47
Table 5-17. Input Timing Specifications ...............................................................................................................................47
Table 5-18. Output Timing Specifications.............................................................................................................................47
Table 5-19. NSMI Output Clock Specifications ....................................................................................................................47
Table 5-20. NSMI Input Timing Specifications .....................................................................................................................48
Table 5-21. NSMI Output Timing Specifications...................................................................................................................48
Table 5-22. CHI Interface Clock Specifications ....................................................................................................................48
Table 5-23. CHI Interface Input Timing Specifications .........................................................................................................48
Table 5-24. CHI Interface Output Timing Specifications ......................................................................................................48
Table 5-25. PSB Interface Clock Specifications ...................................................................................................................49
Table 5-26. PSB Interface Input Timing Specifications ........................................................................................................49
Table 5-27. PSB Interface Output Timing Specifications .....................................................................................................49
Agere Systems Inc.
3
TMXF28155
Supermapper
155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
Hardware Design Guide, Revision 1
May 26, 2006
Table of Contents
(continued)
Tables
Page
Table 5-28. Framer DS1/E1 Interface Clock Specifications .................................................................................................50
Table 5-29. Framer DS1/E1 Interface Input Timing Specifications ......................................................................................50
Table 5-30. Framer DS1/E1 Interface Output Timing Specifications....................................................................................50
Table 5-31. DJA DS1/E1 Interface Clock Specifications .....................................................................................................51
Table 5-32. DJA DS1/E1 Interface Input Timing Specifications ...........................................................................................51
Table 5-33. DJA DS1/E1 Interface Output Timing Specifications ........................................................................................51
Table 5-34. M13 DS1/E1 Interface Clock Specifications .....................................................................................................52
Table 5-35. M13 DS1/E1 Interface Input Timing Specifications ...........................................................................................52
Table 5-36. M13 DS1/E1 Interface Output Timing Specifications ........................................................................................52
Table 5-37. Microprocessor Interface Synchronous Write Cycle Specifications ..................................................................53
Table 5-38. Microprocessor Interface Synchronous Read Cycle Specifications ..................................................................54
Table 5-39. Microprocessor Interface Asynchronous Write Cycle Specifications ................................................................56
Table 5-40. Microprocessor Interface Asynchronous Read Cycle Specifications ................................................................58
Table 5-41. Input Timing Specifications ...............................................................................................................................58
Table 5-42. Output Timing Specifications.............................................................................................................................58
Table 6-1. Telecom Bus Pins ...............................................................................................................................................59
Table 9-1. Document Changes.............................................................................................................................................63
4
Agere Systems Inc.
Hardware Design Guide, Revision 1
May 26, 2006
TMXF28155
Supermapper
155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
Table of Contents
(continued)
Figures
Page
Figure 1-1. Supermapper Block Diagram and High-Level Interface Definition.......................................................................1
Figure 2-1. Pin Diagram of 456-Pin PBGA (Bottom View) .....................................................................................................6
Figure 2-2. Protection Switch ...............................................................................................................................................14
Figure 2-3. DS1/E1 to DXC Block Diagram..........................................................................................................................21
Figure 4-1. Single-Ended Input Specification .......................................................................................................................36
Figure 5-1. Generic Clock Timing.........................................................................................................................................38
Figure 5-2. Generic Interface Data Timing ...........................................................................................................................40
Figure 5-3. DS3DATAOUTCLK Timing ................................................................................................................................42
Figure 5-4. VT Mapper Transmit Path Overhead Detailed Timing .......................................................................................44
Figure 5-5. VT Mapper Receive Path Overhead Detailed Timing ........................................................................................44
Figure 5-6. CHI Transmit I/O Timing ....................................................................................................................................45
Figure 5-7. CHI Receive I/O Timing .....................................................................................................................................45
Figure 5-8. Parallel System Bus Interface Transmit I/O Timing ...........................................................................................46
Figure 5-9. Parallel System Bus Interface Receive I/O Timing ............................................................................................46
Figure 5-10. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin AD17) = 1) ............................................53
Figure 5-11. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin AD17) = 1)............................................54
Figure 5-12. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin AC18) = 0) .......................55
Figure 5-13. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin AC18) = 0) ..........................................57
Figure 6-1. Receive Telecom Bus Timing Diagram for STS-3/STM-1 Signals.....................................................................60
Figure 6-2. Transmit Telecom Bus Timing Diagram for STS-3/STM-1 Signals....................................................................60
Agere Systems Inc.
5
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