SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
Rev. 05 — 6 August 2009
Product data sheet
1. General description
The NXP Semiconductors SE97 measures temperature from
−40 °C
to +125
°C
with
JEDEC Grade B
±1 °C
accuracy between +75
°C
and +95
°C
and also provide 256 bytes
of EEPROM memory communicating via the I
2
C-bus/SMBus. It is typically mounted on a
Dual In-line Memory Module (DIMM) measuring the DRAM temperature in accordance
with the new JEDEC (JC-42.4)
Mobile Platform Memory Module Temperature Sensor
Component
specification and also replacing the Serial Presence Detect (SPD) which is
used to store memory module and vendor information.
The SE97 thermal sensor operates over the V
DD
range of 3.0 V to 3.6 V and the EEPROM
over the range of 3.0 V to 3.6 V write and 1.7 V to 3.6 V read.
Placing the Temp Sensor (TS) on a DIMM allows accurate monitoring of the DIMM module
temperature to better estimate the DRAM case temperature (T
case
) to prevent it from
exceeding the maximum operating temperature of 85
°C.
The chip set throttles the
memory traffic based on the actual temperatures instead of the calculated worst-case
temperature or the ambient temperature using a temp sensor mounted on the
motherboard. There is up to 30 % improvement in thin and light notebooks that are using
one or two 1 GB SO-DIMM modules. The TS is required on DDR3 RDIMM and RDIMM
ECC. Future uses of the TS will include more dynamic control over thermal throttling, the
ability to use the Alarm Window to create multiple temperature zones for dynamic
throttling and to save processor time by scaling the memory refresh rate.
The TS consists of a
∆Σ
Analog-to-Digital Converter (ADC) that monitors and updates its
own temperature readings 10 times per second, converts the reading to a digital data, and
latches them into the data temperature register. User-programmable registers, the
specification of upper/lower alarm and critical temperature trip points, EVENT output
control, and temperature shutdown, provide flexibility for DIMM temperature-sensing
applications.
When the temperature changes beyond the specified boundary limits, the SE97 outputs
an EVENT signal using an open-drain output that can be pulled up between 0.9 V and
3.6 V. The user has the option of setting the EVENT output signal polarity as either an
active LOW or active HIGH comparator output for thermostat operation, or as a
temperature event interrupt output for microprocessor-based systems. The EVENT output
can even be configured as a critical temperature output.
The EEPROM is designed specifically for DRAM DIMMs SPD. The lower 128 bytes
(address 00h to 7Fh) can be Permanent Write Protected (PWP) or Reversible Write
Protected (RWP) by software. This allows DRAM vendor and product information to be
stored and write protected. The upper 128 bytes (address 80h to FFh) are not write
protected and can be used for general purpose data storage.
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
The SE97 has a single die for both the temp sensor and EEPROM for higher reliability and
supports the industry-standard 2-wire I
2
C-bus/SMBus serial interface. The SMBus
TIMEOUT function is supported to prevent system lock-ups. Manufacturer and Device ID
registers provide the ability to confirm the identity of the device. Three address pins allow
up to eight devices to be controlled on a single bus.
2. Features
2.1 General features
I
JEDEC (JC-42.4) TSE 2002B3 DIMM
±
0.5
°C
(typ.) between 75
°C
and 95
°C
temperature sensor plus 256-byte serial EEPROM for Serial Presence Detect (SPD)
I
Optimized for voltage range: 3.0 V to 3.6 V, but SPD can be read down to 1.7 V
I
Shutdown current: 0.1
µA
(typ.) and 5.0
µA
(max.)
I
2-wire interface: I
2
C-bus/SMBus compatible, 0 Hz to 400 kHz
I
SMBus Alert Response Address and TIMEOUT (programmable)
I
ESD protection exceeds 2500 V HBM per JESD22-A114, 250 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Available packages: TSSOP8, HVSON8, HXSON8, HWSON8 (JEDEC PSON8
VCED-3)
2.2 Temperature sensor features
I
I
I
I
I
11-bit ADC Temperature-to-Digital converter with 0.125
°C
resolution
Operating current: 250
µA
(typ.) and 400
µA
(max.)
Programmable hysteresis threshold: off, 0
°C,
1.5
°C,
3
°C,
6
°C
Over/under/critical temperature EVENT output
B grade accuracy:
N
±0.5 °C/±1 °C
(typ./max.)
→
+75
°C
to +95
°C
N
±1.0 °C/±2 °C
(typ./max.)
→
+40
°C
to +125
°C
N
±2.0 °C/±3 °C
(typ./max.)
→ −40 °C
to +125
°C
2.3 Serial EEPROM features
I
Operating current:
N
Write
→
0.6 mA (typ.) for 3.5 ms (typ.)
N
Read
→
100
µA
(typ.)
I
Organized as 1 block of 256 bytes [(256
×
8) bits]
I
100,000 write/erase cycles and 10 years of data retention
I
Permanent and Reversible Software Write Protect
I
Software Write Protection for the lower 128 bytes
SE97_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 6 August 2009
2 of 54
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
3. Applications
I
I
I
I
DDR2 and DDR3 memory modules
Laptops, personal computers and servers
Enterprise networking
Hard disk drives and other PC peripherals
4. Ordering information
Table 1.
Ordering information
Topside
mark
SE97
SE97
97L
S97
Package
Name
TSSOP8
HVSON8
HXSON8
HWSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 4.4 mm
plastic thermal enhanced very thin small outline package;
no leads; 8 terminals; body 3
×
3
×
0.85 mm
plastic thermal enhanced extremely thin small outline package;
no leads; 8 terminals; body 2
×
3
×
0.5 mm
plastic thermal enhanced very very thin small outline package;
no leads; 8 terminals; body 2
×
3
×
0.8 mm
Version
SOT530-1
SOT908-1
SOT1052-1
SOT1069-1
Type number
SE97PW
SE97TK
SE97TL
[1]
SE97TP
[1][2]
[1]
[2]
SE97TL and SE97TP offer improved V
POR
/EVENT I
OL
.
Industry standard 2 mm
×
3 mm
×
0.8 mm package to JEDEC VCED-3 PSON8 in 8 mm
×
4 mm pitch tape 4 k quantity reels.
SE97_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 6 August 2009
3 of 54
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
5. Block diagram
SE97
TEMPERATURE REGISTER
CRITICAL ALARM TRIP
UPPER ALARM TRIP
LOWER ALARM TRIP
CAPABILITY
MANUFACTURING ID
DEVICE/REV ID
SMBus TIMEOUT/ALERT
CONFIGURATION
•
•
•
•
•
•
•
HYSTERESIS
SHUT DOWN TEMP SENSOR
LOCK PROTECTION
EVENT OUTPUT ON/OFF
EVENT OUTPUT POLARITY
EVENT OUTPUT STATUS
CLEAR EVENT OUTPUT STATUS
FFh
NO
WRITE PROTECT
80h
7Fh
SOFTWARE
WRITE PROTECT
00h
R
30 kΩ to 800 kΩ
POR
BAND GAP
TEMPERATURE
SENSOR
11-BIT
∆Σ
ADC
V
DD
V
SS
EVENT
SMBus/I
2
C-BUS
INTERFACE
FILTER
SCL
SDA
2-kbit EEPROM
10 V
OVERVOLTAGE
R
30 kΩ to 800 kΩ
A0
A1
R
30 kΩ to 800 kΩ
A2
POINTER REGISTER
002aab349
Fig 1.
Block diagram of SE97
SE97_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 6 August 2009
4 of 54
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
6. Pinning information
6.1 Pinning
terminal 1
index area
A0
A1
A0
A1
A2
V
SS
1
2
3
4
002aab805
1
2
8
7
V
DD
EVENT
SCL
SDA
8
V
DD
EVENT
SCL
SDA
SE97TL
A2
V
SS
3
4
6
5
SE97PW
7
6
5
002aad548
Transparent top view
Fig 2.
Pin configuration for TSSOP8
Fig 3.
Pin configuration for HXSON8
terminal 1
index area
A0
A1
A2
V
SS
1
2
8
7
V
DD
EVENT
SCL
A2
4
5
SDA
V
SS
002aab803
terminal 1
index area
A0
A1
1
2
8
7
V
DD
EVENT
SCL
SDA
SE97TK
3
6
SE97TP
3
4
6
5
002aad768
Transparent top view
Transparent top view
Fig 4.
Pin configuration for HVSON8
Fig 5.
Pin configuration for HWSON8
6.2 Pin description
Table 2.
Symbol
A0
A1
A2
V
SS
SDA
SCL
EVENT
V
DD
Pin description
Pin
1
2
3
4
5
6
7
8
Type
I
I
I
ground
I/O
I
O
power
Description
I
2
C-bus/SMBus slave address bit 0 with internal pull-down. This
input is overvoltage tolerant to support software write protection.
I
2
C-bus/SMBus slave address bit 1 with internal pull-down
I
2
C-bus/SMBus slave address bit 2 with internal pull-down
device ground
SMBus/I
2
C-bus serial data input/output (open-drain). Must have
external pull-up resistor.
SMBus/I
2
C-bus serial clock input/output (open-drain). Must have
external pull-up resistor.
Thermal alarm output for high/low and critical temperature limit
(open-drain). Must have external pull-up resistor.
device power supply (3.0 V to 3.6 V); supports 1.7 V for
EEPROM read only.
SE97_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 6 August 2009
5 of 54
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