CAT9554, CAT9554A
8-bit I
2
C and SMBus I/O Port with Interrupt
FEATURES
I
400kHz I
2
C bus compatible*
I
2.3V to 5.5V operation
I
Low stand-by current
I
5V tolerant I/Os
I
8 I/O pins that default to inputs at power-up
I
High drive capability
I
Individual I/O configuration
I
Polarity inversion register
I
Active low interrupt output
I
Internal power-on reset
I
No glitch on power-up
I
Noise filter on SDA/SCL inputs
I
Cascadable up to 8 devices
I
Industrial temperature range
I
RoHS-compliant 16-lead SOIC and TSSOP, and
DESCRIPTION
The CAT9554 and CAT9554A are CMOS devices that
provide 8-bit parallel input/output port expansion for I
2
C
and SMBus compatible applications. These I/O
expanders provide a simple solution in applications
where additional I/Os are needed: sensors, power
switches, LEDs, pushbuttons, and fans.
The CAT9554/9554A consist of an input port register, an
output port register, a configuration register, a polarity
inversion register and an I
2
C/SMBus-compatible serial
interface.
Any of the eight I/Os can be configured as an input or
output by writing to the configuration register. The system
master can invert the CAT9554/9554A input data by
writing to the active-high polarity inversion register.
The CAT9554/9554A features an active low interrupt
output which indicates to the system master that an input
state has changed.
The device’s extended addressing capability allows up
to 8 devices to share the same bus. The CAT9554A is
identical to the CAT9554 except the fixed part of the I
2
C
slave address is different. This allows up to 16 of devices
(eight CAT9554 and eight CAT9554A) to be connected
on the same bus.
16-pad TQFN (4 x 4 mm) packages
APPLICATIONS
I
White goods (dishwashers, washing machines)
I
Handheld devices (cell phones, PDAs, digital
cameras)
I
Data Communications (routers, hubs and
servers)
For Ordering Information details, see page 15.
BLOCK DIAGRAM
A0
A1
A2
8-BIT
SCL
SDA
INPUT
FILTER
I2C/SMBUS
CONTROL
WRITE pulse
READ pulse
INPUT/
OUTPUT
PORTS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
VCC
VSS
POWER-ON
RESET
LP
FILTER
I/O7
VCC
INT
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-9002, Rev. C
CAT9554, CAT9554A
PIN CONFIGURATION
SOIC (W)
TSSOP (Y)
A0
A1
A2
I/O0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
SDA
SCL
INT
I/O7
I/O6
I/O5
I/O4
TQFN (HV4)
A1
16
A0
15
VCC SDA
14
13
A2 1
I/O0 2
I/O1 3
I/O2 4
5
6
7
8
12 SCL
11
INT
10 I/O7
9 I/O6
I/O3 VSS I/O4 I/O5
4 x 4 mm
Top View
PIN DESCRIPTION
SOIC / TSSOP
1
2
3
4-7
8
9-12
13
14
15
16
TQFN
15
16
1
2-5
6
7-10
11
12
13
14
PIN NAME
A
0
A
1
A
2
I/O
0-3
V
SS
I/O
4-7
I NT
SCL
SDA
V
CC
FUNCTION
Address Input 0
Address Input 1
Address Input 2
Input/Output Port 0 to Input/Output Port 3
Ground
Input/Output Port 4 to Input/Output Port 7
Interrupt Output (open drain)
Serial Clock
Serial Data
Power Supply
ABSOLUTE MAXIMUM RATINGS
(1)
V
CC
with Respect to Ground ............... –0.5V to +6.5V
Voltage on Any Pin with
Respect to Ground ........................ –0.5V to +5.5V
DC Current on I/O
0
to I/O
7 ...........................................
+50 mA
DC Input Current ............................................. +20 mA
V
CC
Supply Current ............................................ 85mA
RELIABILITY CHARACTERISTICS
Symbol
VZAP
(2)
ILTH
(2)(3)
Parameter
ESD Susceptibility
Latch-up
Reference Test Method
JEDEC Standard JESD 22
JEDEC Standard 17
Min
2000
100
Units
Volts
mA
V
SS
Supply Current .......................................... 100mA
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Junction Temperature ..................................... +150°C
Storage Temperature ........................ -65°C to +150°C
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to V
CC
+1V.
Doc. No. MD-9002, Rev. C
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT9554, CAT9554A
D.C. OPERATING CHARACTERISTICS
V
CC
= 2.3 to 5.5 V; T
A
= -40°C to +85°C, unless otherwise specified
Symbol Parameter
Supplies
V
CC
I
CC
I
stbl
I
stbh
V
POR
V
IL (1)
V
IH (1)
I
OL
I
L
C
I (2)
C
O (2)
A
0
, A
1
, A
2
V
IL (1)
V
IH (1)
I
LI
I/Os
V
IL
V
IH
Low level input voltage
High level input voltage
V
OL
= 0.5 V; V
CC
= 2.3 V;
(3)
V
OL
= 0.7 V; V
CC
= 2.3 V;
(3)
V
OL
= 0.5 V; V
CC
= 4.5 V;
(3)
V
OL
= 0.7 V; V
CC
= 4.5 V;
(3)
V
OL
= 0.5 V; V
CC
= 3.0 V; (
(3)
V
OL
= 0.7 V; V
CC
= 3.0 V;
(3)
I
OH
= – 8 mA; V
CC
= 2.3 V;
(4)
I
OH
= – 10 mA; V
CC
= 2.3 V;
(4)
I
OH
= – 8 mA; V
CC
= 3.0 V;
(4)
I
OH
= – 10 mA; V
CC
= 3.0 V;
(4)
I
OH
= – 8 mA; V
CC
= 4.75 V;
(4)
I
OH
= – 10 mA; V
CC
= 4.75 V;
(4)
V
CC
= 3.6 V; V
I
= V
CC
V
CC
= 5.5 V; V
I
= V
SS
-0.5
2.0
8
10
8
10
8
10
1.8
1.7
2.6
2.5
4.1
4.0
—
—
—
—
—
—
10
13
17
24
14
19
—
—
—
—
—
—
—
—
—
—
0.8
5.5
—
—
—
—
—
—
—
—
—
—
—
—
1
-100
5
8
V
V
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
µA
µA
pF
pF
Low level input voltage
High level input voltage
Input leakage current
-0.5
2.0
-1
—
—
—
0.8
5.5
1
V
V
µA
Supply voltage
Supply current
Standby current
Standby current
Power-on reset voltage
Low level input voltage
High level input voltage
Low level output current
Leakage current
Input capacitance
Output capacitance
Operating mode; V
CC
= 5.5 V; no load;
f
SCL
= 100 kHz
Standby mode; V
CC
= 5.5 V; no load;
V
I
= V
SS
; f
SCL
= 0 kHz; I/O = inputs
Standby mode; V
CC
= 5.5 V; no load;
V
I
= V
CC
; f
SCL
= 0 kHz; I/O = inputs
No load; V
I
= V
CC
or V
SS
2.3
—
—
—
—
-0.5
0.7 V
CC
3
– 1
—
—
—
104
550
0.25
1.5
—
—
—
—
—
—
5.5
175
700
1
1.65
0.3 V
CC
5.5
—
+1
6
8
V
µA
µA
µA
V
V
V
mA
µA
pF
pF
Conditions
Min
Typ
Max
Unit
SCL, SDA,
INT
V
OL
= 0.4V
V
I
= V
CC
or V
SS
V
I
= V
SS
V
O
= V
SS
I
OL
Low level output current
V
OH
High level output voltage
I
IH
I
IL
C
I (2)
C
O (2)
Input leakage current
Input leakage current
Input capacitance
Output capacitance
Notes:
1. V
IL
min and V
IH
max are reference values only and are not tested.
2. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
3. The total current sunk by all I/Os must be limited to 100 mA and each I/O limited to 25 mA maximum.
4. The total current sourced by all I/Os must be limited to 85 mA.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-9002, Rev. C
CAT9554, CAT9554A
A.C. CHARACTERISTICS
V
CC
= 2.3V to 5.5V, T
A
= -40°C to +85°C, unless otherwise specified
(1)
.
Symbol
f
SCL
t
SP
t
LOW
t
HIGH
t
R(2)
t
F(2)
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
AA
t
DH
t
BUF(2)
Port Timing
t
PV
t
PS
t
PH
t
IV
t
IR
Parameter
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
Data In Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a New Transmission Can Start
Output Data Valid
Input Data Setup Time
Input Data Hold Time
Min
Max
400
50
Units
kHz
ns
µs
µs
1.3
0.6
20
20
0.6
0.6
0
100
0.6
900
50
1.3
200
100
1
300
300
ns
ns
µs
µs
ns
ns
µs
ns
ns
µs
ns
ns
µs
Interrupt Timing
Interrupt Valid
Interrupt Reset
4
4
µs
µs
Notes:
1. Test conditions according to "AC Test Conditions" table.
2. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
Doc. No. MD-9002, Rev. C
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT9554, CAT9554A
AC TEST CONDITIONS
Input Rise and Fall time
CMOS Input Voltages
CMOS Input Reference Voltages
TTL Input Voltages
TTL Input Reference Voltages
Output Reference Voltages
Output Load: SDA, INT
Output Load: I/Os
< = 10ns
0.2V
CC
to 0.8V
CC
0.3V
CC
to 0.7V
CC
0.4V to 2.4V
0.8V, 2.0V
0.5V
CC
Current Souce I
OL
= 3mA; C
L
= 100pF
Current Source: I
OL
/I
OH
= 10mA; C
L
= 50pF
tF
tLOW
SCL
tSU:STA
tHD:STA
tHIGH
tLOW
tR
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
SDA OUT
tDH
tBUF
Figure 1. 2-Wire Serial Interface Timing
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-9002, Rev. C
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