3.3 VOLT CMOS SyncFIFO
TM
64 x 36
FEATURES:
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IDT72V3611
•
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64 x 36 storage capacity
Supports clock frequencies up to 67MHz
Fast access times of 10ns
Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
Synchronous data buffering from Port A to Port B
Mailbox bypass register in each direction
Programmable Almost-Full (AF) and Almost-Empty (AE) flags
Microprocessor Interface Control Logic
Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA
Empty Flag (EF) and Almost-Empty (AE) flags synchronized by
CLKB
Passive parity checking on each Port
Parity Generation can be selected for each Port
Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving
120-pin Thin Quad Flatpack (PF)
Industrial temperature range (–40°C to +85°C) is available
°
°
Pin and functionally compatible version of the 5V operating
IDT723611
Green parts available, see ordering information
DESCRIPTION:
The IDT72V3611 is a pin and functionally compatible version of the
IDT723611, designed to run off a 3.3V supply for exceptionally low power
consumption. This device is a monolithic, high-speed, low-power, CMOS
Synchronous (clocked) FIFO memory which supports clock frequencies up to
67MHz and has read access times as fast as 10ns. The 64 x 36 dual-port FIFO
buffers data from Port A to Port B. The FIFO operates in IDT Standard mode
and has flags to indicate empty and full conditions, and two programmable flags,
Almost-Full (AF) and Almost-Empty (AE), to indicate when a selected number
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Parity
Gen/Check
MBF1
PEFB
PGB
Parity
Generation
Output
Register
RST
ODD/
EVEN
Mail 1
Register
Input
Register
Reset
Logic
RAM
ARRAY
64 x 36
36
36
A
0
- A
35
Write
Pointer
Read
Pointer
B
0
- B
35
EF
AE
FF
AF
FIFO
Status
JUNE 7 , 2005
Flag
Logic
Programmable
Flag Offset
Registers
FS
0
FS
1
PGA
PEFA
MBF2
Parity
Gen/Check
Mail 2
Register
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
4657 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEBRUARY 2009
DSC-4657/3
1
©2009
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V3611 3.3V, CMOS SyncFIFO
TM
64 x 36
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
of words is stored in memory. Communication between each port can take place
through two 36-bit mailbox registers. Each mailbox register has a flag to signal
when new mail has been stored. Parity is checked passively on each port and
may be ignored if not desired. Parity generation can be selected for data read
from each port. Two or more devices may be used in parallel to create wider
data paths.
The IDT72V3611 is a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
The Full Flag (FF) and Almost-Full (AF) flag of the FIFO are two-stage
synchronized to the port clock that writes data into its array (CLKA). The Empty
Flag (EF) and Almost-Empty (AE) flag of the FIFO are two-stage synchronized
to the port clock that reads data from its array.
The IDT72V3611 is characterized for operation from 0°C to 70°C. Industrial
temperature range (–40°C to +85°C) is available by special order. This device
is fabricated using IDT's high speed, submicron CMOS technology.
PIN CONFIGURATION
A
24
A
25
A
26
V
CC
A
27
A
28
A
29
GND
A
30
A
31
A
32
A
33
A
34
A
35
GND
B
35
B
34
B
33
B
32
B
31
B
30
GND
B
29
B
28
B
27
V
CC
B
26
B
25
B
24
B
23
A
23
A
22
A
21
GND
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
GND
A
9
A
8
A
7
V
CC
A
6
A
5
A
4
A
3
GND
A
2
A
1
A
0
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B
22
B
21
GND
B
20
B
19
B
18
B
17
B
16
B
15
B
14
B
13
B
12
B
11
B
10
GND
B
9
B
8
B
7
V
CC
B
6
B
5
B
4
B
3
GND
B
2
B
1
B
0
EF
AE
NC
AF
FF
CSA
ENA
CLKA
W/RA
V
CC
PGA
PEFA
MBF2
MBA
FS
1
FS
0
ODD/EVEN
RST
GND
NC
NC
NC
NC
MBB
MBF1
PEFB
PGB
V
CC
W/RB
CLKB
ENB
CSB
NC
TQFP (PN120-1, order code: PF)
TOP VIEW
2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
NOTES:
1. Pin 1 identifier in corner.
2. NC = No internal connection
4657 drw 02
FEBRUARY 10, 2009
IDT72V3611 3.3V, CMOS SyncFIFO
TM
64 x 36
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION (CONTINUED)
AF
FF
CSA
ENA
CLKA
W/RA
V
CC
PGA
PEFA
GND
MBF2
MBA
FS
1
FS
0
ODD/EVEN
RST
GND
NC
NC
NC
NC
MBB
MBF1
GND
PEFB
PGB
V
CC
W/RB
CLKB
ENB
CSB
NC
NC
GND
NC
NC
A
0
A
1
A
2
GND
A
3
A
4
A
5
A
6
V
CC
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
13
A
14
GND
A
15
A
16
A
17
A
18
A
19
A
20
GND
A
21
A
22
A
23
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
V
CC
A
24
A
25
A
26
GND
A
27
A
28
A
29
V
CC
A
30
A
31
A
32
GND
A
33
A
34
A
35
GND
B
35
B
34
B
33
GND
B
32
B
31
B
30
V
CC
B
29
B
28
B
27
GND
B
26
B
25
B
24
V
CC
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
GND
AE
EF
B
0
B
1
B
2
GND
B
3
B
4
B
5
B
6
V
CC
B
7
B
8
B
9
GND
B
10
B
11
V
CC
B
12
B
13
B
14
GND
B
15
B
16
B
17
B
18
B
19
B
20
GND
B
21
B
22
B
23
4657 drw 03
NOTES:
1. Electrical pin 1 in center of beveled edge.
2. NC = No internal connection
PQFP (PQ132-1, order code: PQF)
TOP VIEW
3
FEBRUARY 10, 2009
IDT72V3611 3.3V, CMOS SyncFIFO
TM
64 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
A0-A35
AE
AF
B0-B35
CLKA
Name
Port-A Data
Almost-Empty Flag
Almost-Full Flag
Port-B Data.
Port-A Clock
I/O
I/O
O
O
I/O
I
Description
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words
in the FIFO is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
locations in the FIFO is less than or equal to the value in the Offset register, X.
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port-A and can be
asynchronous or coincident to CLKB.
FF
and
AF
are synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port-B and can be
asynchronous or coincident to CLKA.
EF
and
AE
are synchronized to the LOW-to-HIGH
transition of CLKB.
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
The A0-A35 outputs are in the high-impedance state when
CSA
is HIGH.
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
The B0-B35 outputs are in the high-impedance state when
CSB
is HIGH.
CLKB
Port-B Clock
I
CSA
CSB
EF
Port-A Chip Select
Port-B Chip Select
Empty Flag
I
I
O
ENA
ENB
FF
Port-A Enable
Port-B Enable
Full Flag
FS1, FS0
MBA
MBB
Flag-Offset Selects
Port-A Mailbox Select
Port-B Mailbox Select
MBF1
Mail1 Register Flag
MBF2
Mail2 Register Flag
ODD/
EVEN
PEFA
Odd/Even Parity
Select
Port-A Parity Error
Flag
EF
is synchronized to the LOW-to-HIGH transition of CLKB. When
EF
is LOW, the FIFO is empty,
and reads from its memory are disabled. Data can be read from the FIFO to its output register
when
EF
is HIGH.
EF
is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO memory.
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
O
FF
is synchronized to the LOW-to-HIGH transition of CLKA. When
FF
is LOW, the FIFO is full, and
writes to its memory are disabled.
FF
is forced LOW when the device is reset and is set HIGH by
the second LOW-to-HIGH transition of CLKA after reset.
I
The LOW-to-HIGH transition of
RST
latches the values of FS0 and FS1, which loads one of four
preset values into the Almost-Full and Almost-Empty Offset register (X).
I
A HIGH level on MBA chooses a mailbox register for a port-A read or write operation.
I
A HIGH level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output,
and a LOW level selects the FIFO output register data for output.
O
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes
to the mail1 register are inhibited while
MBF1
is set LOW.
MBF1
is set HIGH by a LOW-to-HIGH
transition of CLKB when a port-B read is selected and MBB is HIGH.
MBF1
is set HIGH when the
device is reset.
O
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while
MBF2
is LOW.
MBF2
is set HIGH by a LOW-to-HIGH
transition of CLKA when a port-A read is selected and MBA is HIGH.
MBF2
is set HIGH when the
device is reset.
I
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity
generation is enabled for a read operation.
O
When any byte applied to terminals A0-A35 fails parity,
PEFA
is LOW. Bytes are organized as
[Port A) A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the
parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The
parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if
parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by
having
CSA
LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the
PEFA
flag is forced
HIGH regardless of the state of A0-A35 inputs.
4
FEBRUARY 10, 2009
IDT72V3611 3.3V, CMOS SyncFIFO
TM
64 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol
PEFB
Name
Port-B Parity Error
Flag
I/O
O
(Port B)
Description
When any byte applied to terminals B0-B35 fails parity,
PEFB
is LOW. Bytes are organized as
B0-B8, B9-B17, B18-B26, B27-B35, with the most significant bit of each byte serving as the parity
bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity
trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by
having
CSB
LOW, ENB HIGH, W/RB LOW, MBB HIGH, and PGB HIGH, the
PEFB
flag is forced
HIGH regardless of the state of the B0-B35 inputs
Parity is generated for mail2 register reads from port A when PGA is HIGH. The type of parity
generated is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8,
A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit
of each byte.
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated
is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17,
B18-B26, and B27-B35. The generated parity bits are output in the most significant bit of
each byte.
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of
CLKB must occur while
RST
is LOW. This sets the
AF, MBF1,
and
MBF2
flags HIGH and the
EF, AE,
and
FF
flags LOW. The LOW-to-HIGH transition of
RST
latches the status of the FS1
and FS0 inputs to select Almost-Full and Almost-Empty flag offset.
A HIGH selects a write operation and a LOW selects a read operation on port A for a
LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state
when W/RA is HIGH.
A HIGH selects a write operation and a LOW selects a read operation on port B for a
LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state
when W/RB is HIGH.
PGA
Port-A Parity
Generation
I
PGB
Port-B Parity
Generation
I
RST
Reset
I
W/RA
Port-A Write/Read
Select
Port-B Write/Read
Select
I
W/RB
I
5
FEBRUARY 10, 2009
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