CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
V
CC
= 5V
±10%;
T
A
= -40
o
C to +85
o
C (HM-6514S-9, HM-6514B-9, HM-6514-9)
T
A
= -55
o
C to +125
o
C (HM-6514B-8, HM-6514-8)
LIMITS
SYMBOL
ICCSB
PARAMETER
Standby Supply Current
HM-6514-9
HM-6514-8
MIN
-
-
-
MAX
25
50
7
UNITS
µA
µA
mA
µA
µA
V
µA
µA
V
V
V
V
V
TEST CONDITIONS
IO = 0mA, E = V
CC
-0.3V, V
CC
= 5.5V
ICCOP
Operating Supply Current (Note 1)
E = 1MHz, IO = 0mA, VI = GND,
V
CC
= 5.5V
IO = 0mA, V
CC
= 2.0V, E = V
CC
ICCDR
Data Retention Supply
Current
HM-6514-9
HM-6514-8
-
-
2.0
-1.0
-1.0
-0.3
V
CC
-2.0
-
2.4
V
CC
-0.4
15
25
-
+1.0
+1.0
0.8
V
CC
+0.3
0.4
-
-
VCCDR
II
IIOZ
VIL
VIH
VOL
VOH1
VOH2
Data Retention Supply Voltage
Input Leakage Current
Input/Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage (Note 2)
T
A
= +25
o
C
PARAMETER
Input Capacitance (Note 2)
Input/Output Capacitance (Note 2)
VI = V
CC
or GND, V
CC
= 5.5V
VIO = V
CC
or GND, V
CC
= 5.5V
V
CC
= 4.5V
V
CC
= 5.5V
IO = 2.0mA, V
CC
= 4.5V
IO = -1.0mA, V
CC
= 4.5V
IO = -100µA, V
CC
= 4.5V
Capacitance
SYMBOL
CI
CIO
NOTES:
MAX
8
10
UNITS
pF
pF
TEST CONDITIONS
f = 1MHz, All measurements are
referenced to device GND
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
6-3
HM-6514
AC Electrical Specifications
V
CC
= 5V
±10%;
T
A
= -40
o
C to +85
o
C (HM-6514S-9, HM-6514B-9, HM-6514-9)
T
A
= -55
o
C to +125
o
C (HM-6514B-8, HM-6514-8)
LIMITS
HM-6514S-9
SYMBOL
(1)
TELQV
(2)
TAVQV
(3)
TELQX
HM-6514B-9
MIN
-
-
5
MAX
220
220
-
HM-6514-9
MIN
-
-
5
MAX
300
320
-
UNITS
ns
ns
ns
TEST
CONDITIONS
(Notes 1, 3)
(Notes 1, 3, 4)
(Notes 2, 3)
PARAMETER
Chip Enable Access Time
Address Access Time
Chip Enable Output Enable
Time
Chip Enable Output Disable
Time
Chip Enable Pulse Negative
Width
Chip Enable Pulse Positive
Width
Address Setup Time
Address Hold Time
Write Enable Pulse Width
Chip Enable Write Pulse
Setup Time
Chip Enable Write Pulse Hold
Time
Data Setup Time
Data Hold Time
Write Data Delay Time
Early Output High-Z Time
Late Output High-Z Time
Read or Write Cycle Time
MIN
-
-
5
MAX
120
120
-
(4)
TEHQZ
-
50
-
80
-
100
ns
(Notes 2, 3)
(5)
TELEH
120
-
200
-
300
-
ns
(Notes 1, 3)
(6)
TEHEL
50
-
90
-
120
-
ns
(Notes 1, 3)
(7)
TAVEL
(8)
TELAX
(9)
TWLWH
(10)
TWLEH
0
40
120
120
-
-
-
-
20
50
200
200
-
-
-
-
20
50
300
300
-
-
-
-
ns
ns
ns
ns
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(11)
TELWH
120
-
200
-
300
-
ns
(Notes 1, 3)
(12)
TDVWH
(13)
TWHDX
(14)
TWLDV
(15)
TWLEL
(16)
TEHWH
(17)
TELEL
50
0
70
0
0
170
-
-
-
-
-
-
120
0
80
0
0
290
-
-
-
-
-
-
200
0
100
0
0
420
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
NOTES:
1. Input pulse levels: 0.8V to V
CC
- 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, C
L
= 50pF (min) - for C
L
greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. V
CC
= 4.5V and 5.5V.
4. TAVQV = TELQV + TAVEL.
6-4
HM-6514
Timing Waveforms
(2) TAVQV
(7)
TAVEL
A
(6)
TEHEL
E
(1) TELQV
DQ
W
TIME
REFERENCE
-1
0
1
2
3
4
5
HIGH Z
(3) TELQX
(4) TEHQZ
VALID DATA OUT
HIGH Z
(8)
TELAX
VALID ADD
(2) TAVQY
(5) TELEH
(17) TELEL
(7) TAVEL
NEXT ADD
(6)
TEHEL
FIGURE 1. READ CYCLE
TRUTH TABLE
INPUTS
TIME
REFERENCE
-1
0
1
2
3
4
5
H
L
L
E
H
W
X
H
H
H
H
X
H
A
X
V
X
X
X
X
V
DATA I/O
DQ
Z
Z
X
V
V
Z
Z
Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Read Accomplished
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
FUNCTION
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
enabled, but data is not valid until during time (T = 2). W
must remain high throughout the read cycle. After the output
data has been read, E may return high (T = 3). This will dis-
able the output buffer and all inputs, and ready the RAM for
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