Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
FEATURES
•
Wide supply voltage range from 1.2 to 3.6 V
•
Inputs accept voltages up to 5.5 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Demultiplexing capability
•
Two independent 2-to-4 decoders
•
Multifunction capability
•
Active LOW mutually exclusive outputs
•
Output drive capability 50
Ω
transmission lines at 85
°C
•
In accordance with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
nA to nY
n
nE to nY
n
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
input capacitance
PARAMETER
propagation delay
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
3.3
3.2
5.0
DESCRIPTION
74LVC139
The 74LVC139 is a high-performance, low-voltage and
low-power Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The 74LVC139 is a dual 2-to-4 line decoder/demultiplexer.
This device has two independent decoders, each
accepting two binary weighted inputs (nA
0
and nA
1
) and
providing four mutually exclusive active LOW outputs
(nY
0
to nY
3
). Each decoder has an active LOW input (nE).
When nE is HIGH, every output is forced HIGH. The
enable input can be used as the data input for a 1-to-4
demultiplexer application.
TYPICAL
ns
ns
pF
pF
UNIT
power dissipation capacitance per multiplexer V
CC
= 3.3 V; notes 1 and 2 36
2003 May 19
2
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1E
1A
0
1A
1
1Y
0
1Y
1
1Y
2
1Y
3
GND
2Y
3
2Y
2
2Y
1
2Y
0
2A
1
2A
0
2E
V
CC
SYMBOL
enable input (active LOW)
address input
address input
output (active LOW)
output (active LOW)
output (active LOW)
output (active LOW)
ground (0 V)
output (active LOW)
output (active LOW)
output (active LOW)
output (active LOW)
address input
address input
enable input (active LOW)
positive supply voltage
DESCRIPTION
74LVC139
handbook, halfpage
1E
1
VCC
16
15
14
13
2E
2A0
2A1
2Y0
2Y1
2Y2
handbook, halfpage
1E 1
1A0 2
1A1 3
1Y0 4
1Y1 5
1Y2 6
1Y3 7
GND 8
MNA778
16 VCC
15 2E
14 2A0
1A0
1A1
1Y0
1Y1
1Y2
1Y3
2
3
4
139
13 2A1
5
6
7
GND
(1)
12
11
10
8
Top view
GND
9
2Y3
MNA972
12 2Y0
11 2Y1
10 2Y2
9 2Y3
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO16 and (T)SSOP16.
Fig.2 Pin configuration DHVQFN16.
2003 May 19
4
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