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74LVC138A
3-to-8 line decoder/demultiplexer; inverting
Rev. 5 — 19 October 2011
Product data sheet
1. General description
The 74LVC138A is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted
address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive
outputs (Y0 to Y7) that are LOW when selected.
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).
Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74LVC138A devices and one inverter. The
74LVC138A can be used as an eight output demultiplexer by using one of the active LOW
enable inputs as the data input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their appropriate active HIGH or LOW state.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Mutually exclusive outputs
Output drive capability 50
transmission lines at 125
C
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74LVC138A
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC138AD
74LVC138ADB
40 C
to +125
C
40 C
to +125
C
Name
SO16
SSOP16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
Type number
74LVC138APW
40 C
to +125
C
74LVC138ABQ
40 C
to +125
C
DHVQFN16 plastic dual in-line compatible thermal-enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
4. Functional diagram
DX
1
1
2
3
A0
A1
A2
Y0
Y1
Y2
Y3
4
5
6
E1
E2
E3
Y4
Y5
Y6
Y7
mna370
0
1
15
14
13
12
11
10
9
7
4
5
6
&
1
2
3
1
2
4
X/Y
0
1
2
3
4
5
6
15
14
13
12
11
10
9
7
0
G
2
0
7
15
14
13
12
11
10
9
7
2
3
2
3
4
4
5
6
&
5
6
7
EN
7
mna371
(a)
(b)
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Y0
1
2
3
A0
A1
A2
3-to-8
DECODER
ENABLE
EXITING
Y1
Y2
Y3
Y4
Y5
Y6
Y7
4
5
6
E1
E2
E3
mna372
15
14
13
12
11
10
9
7
Fig 3.
74LVC138A
Functional diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 19 October 2011
2 of 16
NXP Semiconductors
74LVC138A
3-to-8 line decoder/demultiplexer; inverting
5. Pinning information
5.1 Pinning
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
8
GND
Y6
9
A0
A1
A2
E1
E2
E3
Y7
GND
1
2
3
4
16 V
CC
15 Y0
terminal 1
index area
A1
2
3
4
5
6
7
14 Y1
13 Y2
A2
E1
E2
E3
138
5
6
7
8
001aad033
12 Y3
11 Y4
10 Y5
9
Y6
GND
(1)
Y7
1
A0
138
001aad035
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration for SO16 and (T)SSOP16
Fig 5.
Pin configuration for DHVQFN16
5.2 Pin description
Table 2.
Symbol
A0
A1
A2
E1
E2
E3
GND
Y[0:7]
V
CC
Pin description
Pin
1
2
3
4
5
6
8
15, 14, 13, 12, 11, 10, 9, 7
16
Description
address input
address input
address input
enable input (active LOW)
enable input (active LOW)
enable input (active HIGH)
ground (0 V)
output
supply voltage
74LVC138A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 19 October 2011
3 of 16
NXP Semiconductors
74LVC138A
3-to-8 line decoder/demultiplexer; inverting
6. Functional description
Table 3.
Input
E1
H
X
X
L
E2
X
H
X
L
E3
X
X
L
H
A0
X
X
X
L
H
L
H
L
H
L
H
[1]
Function table
[1]
Output
A1
X
X
X
L
L
H
H
L
L
H
H
A2
X
X
X
L
L
L
L
H
H
H
H
Y0
H
H
H
L
H
H
H
H
H
H
H
Y1
H
H
H
H
L
H
H
H
H
H
H
Y2
H
H
H
H
H
L
H
H
H
H
H
Y3
H
H
H
H
H
H
L
H
H
H
H
Y4
H
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
H
L
H
H
Y6
H
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW state
V
O
= 0 V to V
CC
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO16 packages: above 70
C
the value of P
D
derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60
C
the value of P
D
derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60
C
the value of P
D
derates linearly with 4.5 mW/K.
74LVC138A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 19 October 2011
4 of 16
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