74LV164
8-bit serial-in/parallel-out shift register
Rev. 03 — 4 February 2005
Product data sheet
1. General description
The 74LV164 is a low-voltage, Si-gate CMOS device and is pin and function compatible
with the 74HC164 and 74HCT164.
The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output
from each of the eight stages. Data is entered serially through one of two inputs (DSA or
DSB) and either input can be used as an active HIGH enable for data entry through the
other input. Both inputs must be connected together or an unused input must be tied
HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP)
and enters into Q0, which is the logical AND-function of the two data inputs (DSA and
DSB) that existed one set-up time prior to the rising clock edge.
A LOW on the master reset input (MR) overrides all other inputs and clears the register
asynchronously, forcing all outputs LOW.
2. Features
s
s
s
s
s
s
s
s
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low-voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce): < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°C
Typical V
OHV
(output V
OH
undershoot): > 2 V at V
CC
= 3.3 V and T
amb
= 25
°C
Gated serial data inputs
Asynchronous master reset
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Specified from
−40 °C
to +80
°C
and from
−40 °C
to +125
°C.
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns.
Symbol Parameter
t
PHL
,
t
PLH
propagation delay
CP to Qn
MR to Qn
Conditions
V
CC
= 3.3 V; C
L
= 15 pF
-
-
12
12
-
-
ns
ns
Min
Typ
Max
Unit
Philips Semiconductors
74LV164
8-bit serial-in/parallel-out shift register
Table 1:
Quick reference data
…continued
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns.
Symbol Parameter
f
max
C
I
C
PD
maximum clock
frequency
input capacitance
power dissipation
capacitance per gate
V
CC
= 3.3 V
[1] [2]
Conditions
V
CC
= 3.3 V; C
L
= 15 pF
Min
-
-
-
Typ
78
3.5
40
Max
-
-
-
Unit
MHz
pF
pF
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
The condition is V
I
= GND to V
CC
.
[2]
4. Ordering information
Table 2:
Ordering information
Package
Temperature range Name
74LV164N
74LV164D
74LV164DB
74LV164PW
74LV164BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DIP14
SO14
SSOP14
TSSOP14
DHVQFN14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
SOT762-1
Type number
9397 750 14501
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 February 2005
2 of 21
Philips Semiconductors
74LV164
8-bit serial-in/parallel-out shift register
5. Functional diagram
SRG8
8
9
1
2
C1/
R
3
4
5
6
10
11
12
13
001aac424
DSA
DSB
3
1
2
4
5
6
10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
&
1D
CP
MR
8
9
11
12
13
001aac423
Fig 1. Logic symbol
Fig 2. IEC logic symbol
DSA
DSB
CP
MR
1
2
8
9
3
4
5
6
10
11
12
13
8-BIT SERIAL−IN/PARALLEL−OUT
SHIFT REGISTER
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
001aac425
Fig 3. Functional diagram
9397 750 14501
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 February 2005
3 of 21
Philips Semiconductors
74LV164
8-bit serial-in/parallel-out shift register
6. Pinning information
6.1 Pinning
DSA
2
3
4
5
6
7
GND
CP
8
1
14 V
CC
13 Q7
12 Q6
11 Q5
10 Q4
9
MR
terminal 1
index area
DSA
DSB
Q0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
001aac422
14 V
CC
13 Q7
12 Q6
DSB
Q0
Q1
Q2
Q3
164
V
CC(1)
74LV164
11 Q5
10 Q4
9
8
MR
CP
001aac429
Transparent top view
(1) The die substrate is attached to the
exposed die pad using conductive die
attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration DIP14, SO14,
SSOP14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
6.2 Pin description
Table 3:
Symbol
DSA
DSB
Q0
Q1
Q2
Q3
GND
CP
MR
Q4
Q5
Q6
Q7
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input SA
data input SB
output 0
output 1
output 2
output 3
ground (0 V)
clock input (edge triggered LOW-to-HIGH)
master reset input (active LOW)
output 4
output 5
output 6
output 7
supply voltage
9397 750 14501
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 February 2005
4 of 21
Philips Semiconductors
74LV164
8-bit serial-in/parallel-out shift register
7. Functional description
7.1 Function table
Table 4:
Operating
mode
Reset (clear)
Shift
Function table
[1]
Input
MR
L
H
H
H
H
[1]
Output
CP
X
↑
↑
↑
↑
DSA
X
l
l
h
h
DSB
X
l
h
l
h
Q0
L
L
L
L
H
Q1 to Q7
L to L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
H = HIGH voltage level;
L = LOW voltage level;
↑
= LOW-to-HIGH clock transition;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
q = lower case letter indicates the state of referenced input one set-up time prior to the LOW-to-HIGH CP
transition.
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
I
OK
I
O
I
CC
,
I
GND
T
stg
P
tot
supply voltage
input diode current
output diode current
output source or sink
current
V
CC
or GND current
storage temperature
total power dissipation
DIP14 package
SO14, (T)SSOP14
and DHVQFN14
packages
[1]
[2]
[3]
DIP14 package: P
tot
derates linearly with 12 mW/K above 70
°C.
SO14 package: P
tot
derates linearly with 8 mW/K above 70
°C.
(T)SSOP14 package: P
tot
derates linearly with 5.5 mW/K above 60
°C.
DHVQFN14 package: P
tot
derates linearly with 4.5 mW/K above 60
°C.
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
Min
−0.5
-
-
-
-
−65
Max
+7.0
±20
±50
±25
±50
+150
750
500
Unit
V
mA
mA
mA
mA
°C
mW
mW
T
amb
=
−40 °C
to +125
°C
[2]
[3]
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
9397 750 14501
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 February 2005
5 of 21
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