CD54HC597, CD74HC597,
CD74HCT597
Data sheet acquired from Harris Semiconductor
SCHS191C
January 1998 - Revised October 2003
High-Speed CMOS Logic
8-Bit Shift Register with Input Storage
Description
The ’HC597 and CD74HCT597 are high-speed silicon gate
CMOS devices that are pin-compatible with the LSTTL 597
devices. Each device consists of an 8-flip-flop input register
and an 8-bit parallel-in/serial-in, serial-out shift register. Each
register is controlled by its own clock. A “low” on the parallel
load input (PL) shifts parallel stored data asynchronously into
the shift register. A “low” master input (MR) clears the shift
register. Serial input data can also be synchronously shifted
through the shift register when PL is high.
Features
• Buffered Inputs
[ /Title
(CD74
HC597
,
CD74
HCT59
7)
/Sub-
ject
(High
Speed
CMOS
• Asynchronous Parallel Load
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤
1µA at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC597F3A
CD74HC597E
CD74HC597M
CD74HC597MT
CD74HC597M96
CD74HC597NSR
CD74HCT597E
CD74HCT597M
CD74HCT597MT
CD74HCT597M96
TEMP. RANGE (
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC597
(CERDIP)
CD74HC597
(PDIP, SOIC, SOP)
CD74HCT597
(PDIP, SOIC)
TOP VIEW
D1 1
D2 2
D3 3
D4 4
D5 5
D6 6
D7 7
GND 8
16 V
CC
15 D0
14 D
S
13 PL
12 ST
CP
11 SH
CP
10 MR
9 Q7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
2003, Texas Instruments Incorporated
1
CD54HC597, CD74HC597, CD74HCT597
Functional Diagram
DS
D0
D1
D2
PARALLEL
DATA
INPUTS
D3
D4
D5
D6
D7
ST
CP
SH
CP
PL
MR
15
1
2
3
8 F/F
STORAGE
REG.
5
4
6
7
12
11
13
10
9
Q7
8-BIT
SHIFT
REG.
14
FUNCTION TABLE
ST
CP
↑
↑
No Clock Edge
X
SH
CP
X
X
X
X
PL
X
L
L
L
MR
X
H
H
L
FUNCTION
Data Loaded to Input Flip-Flops
Data Loaded from Inputs to Shift Register
Data Transferred from Input Flip-Flops to Shift Register
Invalid Logic, State of Shift Register Indeterminate when
Signals Removed
Shift Register Cleared
Shift Register Clocked Qn = Qn-1, Q0 = D
S
X
X
X
↑
H
H
L
H
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑
= Transition from Low to High CP Level
2
CD54HC597, CD74HC597, CD74HCT597
Absolute Maximum Ratings
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V.
. . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . .
64
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
4.5
6
Low Level Input
Voltage
V
IL
-
-
2
4.5
6
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
I
V
CC
or
GND
V
OL
V
IH
or V
IL
V
OH
V
IH
or V
IL
-0.02
-0.02
-0.02
-
-4
-5.2
0.02
0.02
0.02
-
4
5.2
-
2
4.5
6
-
4.5
6
2
4.5
6
-
4.5
6
6
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.26
0.26
±0.1
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.84
5.34
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.33
0.33
±1
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.7
5.2
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.4
0.4
±1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
SYMBOL
V
I
(V)
I
O
(mA)
V
CC
(V)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
3
CD54HC597, CD74HC597, CD74HCT597
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Quiescent Device
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
I
I
I
CC
∆I
CC
(Note 2)
V
CC
and
GND
V
CC
or
GND
V
CC
-2.1
V
OL
V
IH
or V
IL
V
IH
V
IL
V
OH
-
-
V
IH
or V
IL
-
-
-0.02
4.5 to
5.5
4.5 to
5.5
4.5
2
-
4.4
-
-
-
-
0.8
-
2
-
4.4
-
0.8
-
2
-
4.4
-
0.8
-
V
V
V
SYMBOL
I
CC
V
I
(V)
V
CC
or
GND
I
O
(mA)
0
25
o
C
MIN
-
TYP
-
MAX
8
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
-
MAX
80
MIN
-
MAX
160
UNITS
µA
V
CC
(V)
6
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0
0
-
5.5
5.5
4.5 to
5.5
-
-
-
-
100
±0.1
8
360
-
-
-
±1
80
450
-
-
-
±1
160
490
µA
µA
µA
HCT Input Loading Table
INPUT
D
S
D
n
PL, MR
ST
CP
, SH
CP
UNIT LOADS
0.2
0.3
1.5
1.5
NOTE: Unit Load is
∆I
CC
limit specified in DC Electrical Specifications
Table, e.g., 360µA max. at 25
o
C.
Prerequisite for Switching Specifications
25
o
C
PARAMETER
HC TYPES
SH
CP
Frequency
f
MAX
2
4.5
6
6
30
35
-
-
-
-
-
-
5
25
29
-
-
-
-
-
-
4
20
23
-
-
-
-
-
-
MHz
MHz
MHz
SYMBOL
V
CC
(V)
MIN
TYP
MAX
-40
o
C TO 85
o
C
MIN
TYP
MAX
-55
o
C TO 125
o
C
MIN
TYP
MAX
UNITS
4
CD54HC597, CD74HC597, CD74HCT597
Prerequisite for Switching Specifications
(Continued)
25
o
C
PARAMETER
SH
CP
Pulse Width
SYMBOL
t
W
V
CC
(V)
2
4.5
6
ST
CP
Pulse Width
t
W
2
4.5
6
MR Pulse Width
t
W
2
4.5
6
PL Pulse Width
t
W
2
4.5
6
ST
CP
to SH
CP
Setup
Time
t
SU
2
4.5
6
D
S
to SH
CP
Setup Time
D
n
to ST
CP
Setup Time
t
SU
2
4.5
6
ST
CP
to SH
CP
Setup
Time
t
H
2
4.5
6
D
S
to SH
CP
Hold Time
D
n
to ST
CP
Hold Time
t
H
2
4.5
6
MR to SH
CP
Removal
Time
t
REM
2
4.5
6
HCT TYPES
SH
CP
Frequency
SH
CP
Pulse Width
ST
CP
Pulse Width
MR Pulse Width
PL Pulse Width
ST
CP
to SH
CP
Setup
Time
f
MAX
t
W
t
W
t
W
t
W
t
SU
4.5
4.5
4.5
4.5
4.5
4.5
25
20
13
18
16
24
-
-
-
-
-
-
-
-
-
-
-
-
20
25
16
23
20
30
-
-
-
-
-
-
-
-
-
-
-
-
16
30
20
27
24
36
-
-
-
-
-
-
-
-
-
-
-
-
MHz
ns
ns
ns
ns
ns
MIN
80
16
14
60
12
10
80
16
14
70
14
12
100
20
17
50
10
9
0
0
0
3
3
3
3
3
3
TYP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-40
o
C TO 85
o
C
MIN
100
20
17
75
15
13
100
20
17
90
18
15
125
25
21
65
13
11
0
0
0
3
3
3
3
3
3
TYP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-55
o
C TO 125
o
C
MIN
120
24
20
90
18
15
120
24
20
105
21
18
150
30
26
75
15
13
0
0
0
3
3
3
3
3
3
TYP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
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