74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
Rev. 1 — 30 January 2013
Product data sheet
1. General description
The 74HC4094-Q100; 74HCT4094-Q100 is an 8-bit serial-in/serial or parallel-out shift
register with a storage register and 3-state outputs. Both the shift and storage register
have separate clocks. The device features a serial input (D) and two serial outputs (QS1
and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP
input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow
cascading when clock edges are fast. The same data is available at QS2 on the next
HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow.
The data in the shift register is transferred to the storage register when the STR input is
HIGH. Data in the storage register appears at the outputs whenever the output enable
input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance
OFF-state. Operation of the OE input does not affect the state of the registers. Inputs
include clamp diodes that enable the use of current limiting resistors to interface inputs to
voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Complies with JEDEC standard JESD7A
Input levels:
For 74HC4094-Q100: CMOS level
For 74HCT4094-Q100: TTL level
Low-power dissipation
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
3. Applications
Serial-to-parallel data conversion
Remote control holding register
NXP Semiconductors
74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4094D-Q100
74HCT4094D-Q100
74HC4094DB-Q100
74HCT4094DB-Q100
74HC4094PW-Q100
40 C
to +125
C
40 C
to +125
C
SSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads; body width
3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT109-1
SOT338-1
SOT403-1
Type number
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
5. Functional diagram
3
CP
1
STR
QS1
QS2
QP0
QP1
QP2
2
D
QP3
QP4
QP5
QP6
QP7
OE
15
7
14
13
12
11
9
10
4
5
6
3
2
1
15
C2
EN3
SRG8
C1/
1D
2D
3
4
5
6
7
14
13
12
11
9
10
001aaf111
001aaf112
Fig 1.
Functional diagram
Fig 2.
Logic symbol
2
3
D
CP
8-STAGE SHIFT
REGISTER
QS2
QS1
STR
8-BIT STORAGE
REGISTER
10
9
1
15
OE
3-STATE OUTPUTS
QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7
4
5
6
7
14
13
12
11
001aaf119
Fig 3.
Logic diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
74HC_HCT4094_Q100
Product data sheet
Rev. 1 — 30 January 2013
2 of 21
NXP Semiconductors
74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
STAGE 0
D
D
CP
FF 0
CP
CP
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
CP
FF 7
D
LE
LATCH
Q
QS2
Q
QS1
D
LE
Q
D
LE
Q
LATCH 0
STR
LATCH 7
OE
QP0
QP1
QP2
QP3
QP4
QP5
QP6
QP7
001aag799
Fig 4.
Logic diagram
6. Pinning information
6.1 Pinning
+& 4
+&7 4
675
'
&3
43
43
43
43
*1'
DDD
9
&&
2(
43
43
43
43
46
46
675
'
&3
43
43
43
43
*1'
+& 4
+&7 4
9
&&
2(
43
43
43
43
46
DDD
46
Fig 5.
Pin configuration SO16
Fig 6.
Pin configuration SSOP16 and TSSOP16
74HC_HCT4094_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 30 January 2013
3 of 21
NXP Semiconductors
74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
6.2 Pin description
Table 2.
Symbol
STR
D
CP
QP0 to QP7
V
SS
QS1, QS2
OE
V
DD
Pin description
Pin
1
2
3
4, 5, 6, 7, 14, 13, 12, 11
8
9, 10
15
16
Description
strobe input
data input
clock input
parallel output
ground supply voltage
serial output
output enable input
supply voltage
7. Functional description
Table 3.
Inputs
CP
[1]
Function table
[1]
Parallel outputs
OE
L
L
H
H
H
H
STR
X
X
L
H
H
H
D
X
X
X
L
H
H
QP0
Z
Z
NC
L
H
NC
QPn
Z
Z
NC
QPn
1
QPn
1
NC
Serial outputs
QS1
Q6S
NC
Q6S
Q6S
Q6S
NC
QS2
NC
Q7S
NC
NC
NC
Q7S
At the positive clock edge, the information in the 7
th
register stage is transferred to the 8
th
register stage and the QSn outputs.
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= positive-going transition;
= negative-going transition;
Z = HIGH-impedance OFF-state; NC = no change;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
OUTPUT QP0
INTERNAL Q6S (FF 6)
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
001aaf117
Z-state
Z-state
Fig 7.
Timing diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
74HC_HCT4094_Q100
Product data sheet
Rev. 1 — 30 January 2013
4 of 21
NXP Semiconductors
74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
-
65
[1]
Max
+7
20
20
25
+50
50
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
-
For SO16: P
tot
derates linearly with 8 mW/K above 70
C.
For SSOP16 and TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC4094-Q100
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT4094-Q100
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
74HC_HCT4094_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 30 January 2013
5 of 21
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