CD54HC194, CD74HC194,
CD74HCT194
Data sheet acquired from Harris Semiconductor
SCHS164G
September 1997 - Revised May 2006
High-Speed CMOS Logic
4-Bit Bidirectional Universal Shift Register
Description
The ’HC194 and CD74HCT194 are 4-bit shift registers with
Asynchronous Master Reset (MR). In the parallel mode (S0
and S1 are high), data is loaded into the associated flip-flop
and appears at the output after the positive transition of the
clock input (CP). During parallel loading serial data flow is
inhibited. Shift left and shift right are accomplished
synchronously on the positive clock edge with serial data
entered at the shift left (DSL) serial input for the shift left
mode, and at the shift right (DSR) serial input for the shift
right mode. Clearing the register is accomplished by a Low
applied to the Master Reset (MR) pin.
Features
[ /Title
(CD74
HC194,
CD74H
CT194)
/Sub-
ject
(High-
Speed
CMOS
Logic
4-Bit
• Four Operating Modes
- Shift Right, Shift Left, Hold and Reset
• Synchronous Parallel or Serial Operation
• Typical f
MAX
= 60MHz at V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
• Asynchronous Master Reset
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤
1µA at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC194F3A
CD74HC194E
CD74HC194M
CD74HC194MT
CD74HC194M96
CD74HC194NSR
CD74HC194PW
CD74HC194PWR
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
Pinout
CD54HC194 (CERDIP)
CD74HC194 (PDIP, SOIC, SOP, TSSOP)
CD74HCT194 (PDIP)
TOP VIEW
MR 1
DSR 2
D
0
3
D
1
4
D
2
5
D
3
6
DSL 7
GND 8
16 V
CC
15 Q
0
14 Q
1
13 Q
2
12 Q
3
11 CP
10 S1
9 S0
CD74HC194PWT
CD74HCT194E
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
2006, Texas Instruments Incorporated
1
CD54HC194, CD74HC194, CD74HCT194
Functional Diagram
D
0
D
1
D
2
D
3
DSL
DSR
S0
S1
MR
CP
3
4
5
6
7
2
9
10
1
11
15
14
13
12
Q
0
Q
1
Q
2
Q
3
GND = 8
V
CC
= 16
TRUTH TABLE
INPUTS
OPERATING
MODE
Reset (Clear)
Hold (Do Nothing)
Shift Left
CP
X
X
↑
↑
Shift Right
↑
↑
Parallel Load
↑
MR
L
H
H
H
H
H
H
S1
X
l
h
h
l
l
h
S0
X
l
l
l
h
h
h
DSR
X
X
X
X
l
h
X
DSL
X
X
l
h
X
X
X
D
n
X
X
X
X
X
X
d
n
Q
0
L
q
0
q
1
q
1
L
H
d
0
OUTPUT
Q
1
L
q
1
q
2
q
2
q
0
q
0
d
1
Q
2
L
q
2
q
3
q
3
q
1
q
1
d
2
Q
3
L
q
3
L
H
q
2
q
2
d
3
H = High Voltage Level,
h = High Voltage Level One Set-up Time Prior To The Low to High Clock Transition,
L = Low Voltage Level,
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition,
d
n
(q
n
) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low To High Clock
Transition,
X = Don’t Care,
↑
= Transition from Low to High Level
2
CD54HC194, CD74HC194, CD74HCT194
Absolute Maximum Ratings
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Package Thermal Impedance,
θ
JA
(see Note 2):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
o
C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
o
C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
o
C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108
o
C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
4.5
6
Low Level Input
Voltage
V
IL
-
-
2
4.5
6
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
-0.02
-0.02
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
-4
-5.2
0.02
0.02
0.02
Low Level Output
Voltage
TTL Loads
4
5.2
2
4.5
6
4.5
6
2
4.5
6
4.5
6
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.26
0.26
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SYMBOL
V
I
(V)
I
O
(mA) V
CC
(V)
MIN
25
o
C
TYP
MAX
-40
o
C TO 85
o
C
MIN
MAX
-55
o
C TO 125
o
C
MIN
MAX
UNITS
3
CD54HC194, CD74HC194, CD74HCT194
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Input Leakage
Current
Quiescent Device
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
I
I
I
CC
∆I
CC
(Note 3)
V
CC
to
GND
V
CC
or
GND
V
CC
-2.1
V
OL
V
IH
or
V
IL
V
IH
V
IL
V
OH
-
-
4.5 to
5.5
4.5 to
5.5
4.5
2
-
-
2
-
2
-
V
SYMBOL
I
I
I
CC
V
I
(V)
V
CC
or
GND
V
CC
or
GND
I
O
(mA) V
CC
(V)
-
6
MIN
-
25
o
C
TYP
-
MAX
±0.1
8
-40
o
C TO 85
o
C
MIN
-
MAX
±1
80
-55
o
C TO 125
o
C
MIN
-
MAX
±1
160
UNITS
µA
µA
0
6
-
-
-
-
-
-
-
-
0.8
-
0.8
-
0.8
V
V
IH
or
V
IL
-0.02
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0
5.5
-
-
±0.1
8
-
±1
80
-
±1
160
µA
µA
µA
0
5.5
-
-
-
-
-
4.5 to
5.5
-
100
360
-
450
-
490
HCT Input Loading Table
INPUT
CP
MR
DSL, DSR, D
n
Sn
UNIT LOADS
0.6
0.55
0.25
1.10
NOTE: Unit Load is
∆I
CC
limit specified in DC Electrical
Specifications table, e.g. 360µA max at 25
o
C.
4
CD54HC194, CD74HC194, CD74HCT194
Prerequisite For Switching Function
25
o
C
PARAMETER
HC TYPES
Max. Clock Frequency
(Figure 1)
f
MAX
-
2
4.5
6
MR Pulse Width
(Figure 2)
t
W
-
2
4.5
6
Clock Pulse Width
(Figure 1)
t
W
-
2
4.5
6
Set-up Time
Data to Clock (Figure 3)
t
SU
-
2
4.5
6
Removal Time,
MR to Clock (Figure 2)
t
REM
-
2
4.5
6
Set-Up Time
S1, S0 to Clock (Figure 4)
t
SU
-
2
4.5
6
Set-up Time
DSL, DSR to Clock (Figure 4)
t
SU
-
2
4.5
6
Hold Time
S1, S0 to Clock (Figure 4)
t
H
-
2
4.5
6
Hold Time
Data to Clock (Figure 3)
t
H
-
2
4.5
6
HCT TYPES
Max. Clock Frequency (Figure 1)
MR Pulse Width (Figure 2)
Clock Pulse Width (Figure 1)
Set-up Time, Data to Clock
(Figure 3)
Removal Time MR to Clock
(Figure 2)
f
MAX
t
W
t
W
t
SU
t
REM
-
-
-
-
4.5
4.5
4.5
4.5
27
16
16
14
-
-
-
-
22
20
20
18
-
-
-
-
18
24
24
21
-
-
-
-
MHz
ns
ns
ns
6
30
35
80
16
14
80
16
14
70
14
12
60
12
10
80
16
14
70
14
12
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
24
28
100
20
17
100
20
17
90
18
15
75
15
13
100
20
17
90
18
15
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
20
23
120
24
20
120
24
20
105
21
19
90
18
15
120
24
20
105
21
18
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
TEST
CONDITIONS V
CC
(V)
MIN
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
-
4.5
12
-
15
-
18
-
ns
5
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