74AHC138-Q100;
74AHCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
Rev. 2 — 2 April 2014
Product data sheet
1. General description
The 74AHC138-Q100; 74AHCT138-Q100 are high-speed Si-gate CMOS devices and are
pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
with JEDEC standard No. 7A.
The 74AHC138-Q100; 74AHCT138-Q100 is a 3-to-8 line decoder/demultiplexer. It
accepts three binary weighted address inputs (A0, A1 and A2). When enabled, it
provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected. There
are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every
output is HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function, allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74AHC138-Q100; 74AHCT138-Q100 devices
and one inverter. The 74AHC138-Q100; 74AHCT138-Q100 can be used as an eight
output demultiplexer by using one of the active LOW enable inputs as the data input and
the remaining enable inputs as strobes. Unused enable inputs must be permanently tied
to their appropriate active HIGH or LOW state.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Balanced propagation delays
All inputs have Schmitt-trigger action
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Inputs accept voltages higher than V
CC
For 74AHC138-Q100 only: operates with CMOS input levels
For 74AHCT138-Q100 only: operates with TTL input levels
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74AHC138-Q100; 74AHCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC138D-Q100
74AHCT138D-Q100
74AHC138PW-Q100
74AHCT138PW-Q100
74AHC138BQ-Q100
74AHCT138BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16
leads; body width 4.4 mm
Version
SOT109-1
SOT403-1
Type number
DHVQFN16 plastic dual in-line compatible thermal-enhanced SOT763-1
very thin quad flat package; no leads; 16
terminals; body 2.5
3.5
0.85 mm
4. Functional diagram
DX
1
1
2
3
A0
A1
A2
Y0
Y1
Y2
Y3
4
5
6
E1
E2
E3
Y4
Y5
Y6
Y7
mna370
0
1
15
14
13
12
11
10
9
7
4
5
6
&
1
2
3
1
2
4
X/Y
0
1
2
3
4
5
6
15
14
13
12
11
10
9
7
0
G
2
0
7
15
14
13
12
11
10
9
7
2
3
2
3
4
4
5
6
&
5
6
7
EN
7
mna371
(a)
(b)
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Y0
1
2
3
A0
A1
A2
3-to-8
DECODER
ENABLE
EXITING
Y1
Y2
Y3
Y4
Y5
Y6
Y7
4
5
6
E1
E2
E3
mna372
15
14
13
12
11
10
9
7
Fig 3.
Functional diagram
74AHC_AHCT138_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 2 April 2014
2 of 17
NXP Semiconductors
74AHC138-Q100; 74AHCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration for SO16 and TSSOP16
Fig 5.
Pin configuration for DHVQFN16
5.2 Pin description
Table 2.
Symbol
A0
A1
A2
E1
E2
E3
GND
Y0 to Y7
V
CC
Pin description
Pin
1
2
3
4
5
6
8
15, 14, 13, 12, 11, 10, 9, 7
16
Description
address input
address input
address input
enable input (active LOW)
enable input (active LOW)
enable input (active HIGH)
ground (0 V)
output
supply voltage
74AHC_AHCT138_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 2 April 2014
3 of 17
NXP Semiconductors
74AHC138-Q100; 74AHCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
6. Functional description
Table 3.
Input
E1
H
X
X
L
L
L
L
L
L
L
L
[1]
Function table
[1]
Output
E2
X
H
X
L
L
L
L
L
L
L
L
E3
X
X
L
H
H
H
H
H
H
H
H
A0
X
X
X
L
H
L
H
L
H
L
H
A1
X
X
X
L
L
H
H
L
L
H
H
A2
X
X
X
L
L
L
L
H
H
H
H
Y0
H
H
H
L
H
H
H
H
H
H
H
Y1
H
H
H
H
L
H
H
H
H
H
H
Y2
H
H
H
H
H
L
H
H
H
H
H
Y3
H
H
H
H
H
H
L
H
H
H
H
Y4
H
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
H
L
H
H
Y6
H
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO16 package
TSSOP16 package
DHVQFN16 package
[1]
[2]
[3]
[4]
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
20
25
75
-
+150
500
500
500
Unit
V
V
mA
mA
mA
mA
mA
C
mW
mW
mW
V
I
<
0.5
V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
20
-
-
-
75
65
T
amb
=
40 C
to +125
C
[2]
[3]
[4]
-
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
C.
P
tot
derates linearly with 5.5 mW/K above 60
C.
P
tot
derates linearly with 4.5 mW/K above 60
C.
74AHC_AHCT138_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 2 April 2014
4 of 17
NXP Semiconductors
74AHC138-Q100; 74AHCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 3.3 V
0.3 V
V
CC
= 5.0 V
0.5 V
Conditions
74AHC138-Q100
Min
2.0
0
0
40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
74AHCT138-Q100
Min
4.5
0
0
40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
-
20
V
V
V
C
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
For type 74AHC138-Q100
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
50 A;
V
CC
= 2.0 V
I
O
=
50 A;
V
CC
= 3.0 V
I
O
=
50 A;
V
CC
= 4.5 V
I
O
=
4.0
mA; V
CC
= 3.0 V
I
O
=
8.0
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 50
A;
V
CC
= 2.0 V
I
O
= 50
A;
V
CC
= 3.0 V
I
O
= 50
A;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V or 5.5 V
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
3.0
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
0.1
4.0
10
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.48
3.8
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.44
0.44
1.0
40
10
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.55
0.55
2.0
80
10
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
pF
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
74AHC_AHCT138_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 2 April 2014
5 of 17
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