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74HC4020; 74HCT4020
14-stage binary ripple counter
Rev. 6 — 3 February 2016
Product data sheet
1. General description
The 74HT4020; 74HCT4020 is a 14-stage binary ripple counter with a clock input (CP), an
overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0,
and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on
MR clears all counter stages and forces all outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop. This device features reduced input threshold
levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this
enables the use of current limiting resistors to interface inputs to voltages in excess of
V
CC
.
2. Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
Input levels:
For 74HC4020: CMOS level
For 74HCT4020: TTL level
Multiple package options
Complies with JEDEC standard no. 7A
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4020D
74HCT4020D
74HC4020DB
74HCT4020DB
40 C
to +125
C
SSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT109-1
Type number
plastic shrink small outline package; 16 leads; body SOT338-1
width 5.3 mm
NXP Semiconductors
74HC4020; 74HCT4020
14-stage binary ripple counter
Table 1.
Ordering information
…continued
Package
Temperature range
Name
TSSOP16
Description
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT403-1
40 C
to +125
C
40 C
to +125
C
Type number
74HC4020PW
74HCT4020PW
74HC4020BQ
74HCT4020BQ
DHVQFN16 plastic dual in-line compatible thermal enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
5. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 6 — 3 February 2016
2 of 19
NXP Semiconductors
74HC4020; 74HCT4020
14-stage binary ripple counter
Fig 4.
Logic diagram
6. Pinning information
6.1 Pinning
(1) The substrate is attached to this pad using conductive
die attach material. It cannot be used as supply pin or
input. It is recommended that no connection is made at
all.
Fig 5.
Pin configuration SO16, SSOP16 and
TSSOP16
Fig 6.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
Q0, Q3 to Q13
GND
CP
MR
V
CC
74HC_HCT4020
Pin description
Pin
9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3
8
10
11
16
Description
output
ground (0 V)
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
positive supply voltage
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 6 — 3 February 2016
3 of 19
NXP Semiconductors
74HC4020; 74HCT4020
14-stage binary ripple counter
7. Functional description
Table 3.
Input
CP
X
[1]
Function table
Output
MR
L
L
H
Q0, Q3 to Q13
no change
count
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW-to-HIGH clock transition;
= HIGH-to-LOW clock transition.
7.1 Timing diagram
Fig 7.
Timing diagram
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 6 — 3 February 2016
4 of 19
FPGA/CPLD
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