INTEGRATED CIRCUITS
74LV4060
14-stage binary ripple counter with
oscillator
Product specification
1998 Jun 23
Philips
Semiconductors
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74LV4060
FEATURES
•
Wide operating voltage: 1.0 to 5.5 V
•
Optimized for Low Voltage applications: 1.0 to 3.6 V
•
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
•
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
•
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V, T
amb
= 25°C.
T
amb
= 25°C.
APPLICATIONS
•
Control Counters
•
Timers
•
Frequency Dividers
•
Time-delay circuits
DESCRIPTION
The 74LV4060 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT4060.
The 74LV4060 is a 14-stage ripple-carry counter/divider and
oscillator with three oscillator terminals (RS, R
TC
and C
TC
), ten
buffered outputs (Q
3
to Q
9
and Q
11
to Q
13
) and an overriding
asynchronous master reset (MR). The oscillator configuration allows
design of either RC or crystal oscillator circuits. The oscillator may
be replaced by an external clock signal at input RS. In this case,
keep the oscillator pins (R
TC
and C
TC
) floating.
The counter advances on the negative-going transition of RS. A
HIGH level on MR resets the counter (Q
3
to Q
9
and Q
11
to
Q
13
= LOW), independent of the other input conditions.
•
All active components on chip
•
RC or crystal oscillator configuration
•
Output capability: standard (except for R
TC
and C
TC
)
•
I
CC
category: MSI
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
<
2.5 ns
SYMBOL
PARAMETER
Propagation delay
RS to Q
3
t
PHL
/t
PLH
t
PHL
f
max
C
1
C
PD
Q
n
to Q
n+1
MR to Q
n
Maximum clock frequency
Input capacitance
Power dissipation capacitance per package
Notes 1, 2 and 3
CONDITIONS
C
L
= 15 pF
V
CC
= 3.3 V
29
6
16
99
3.5
40
MHz
pF
pF
ns
TYPICAL
UNIT
NOTES:
1. C
PD
is used to determine the dynamic power
dissipation (P
D
in
mW)
P
D
= C
PD
x V
CC2
x f
i
+
S
(C
L
x V
CC2
x f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
x V
CC2
x f
o
) = sum of the outputs.
2. The condition is V
1
= GND to V
CC
3. For formula on dynamic power dissipation, see the
following pages.
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV4060 N
74LV4060 D
74LV4060 DB
74LV4060 PW
NORTH AMERICA
74LV4060 N
74LV4060 D
74LV4060 DB
74LV4060PW DH
PKG. DWG. #
SOT38-4
SOT109-1
SOT338-1
SOT403-1
1998 Jun 23
2
853-2076 19619
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74LV4060
PIN DESCRIPTION
PIN NO.
1, 2, 3
7, 5, 4, 6,
15, 13, 15
8
9
10
11
12
16
SYMBOL
Q
11
to Q13
Q
3
to Q
9
GND
C
TC
R
TC
RS
MR
V
CC
FUNCTION
Counter outputs
Counter outputs
Ground (0 V)
External capacitor connection
External resistor connection
Clock input/oscillator pin
Master reset
Positive supply voltage
LOGIC SYMBOL
10
9
R
TC
C
TC
11 RS
12
MR
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q11
Q12
Q13
7
5
4
6
14
13
15
1
2
3
PIN CONFIGURATION
SV00307
Q
11
Q
12
Q
13
Q
5
Q
4
Q
6
Q
3
GND
1
2
3
4
5
6
7
16
15
14
13
12
11
10
9
V
CC
Q
9
Q
7
Q
8
MR
RS
R
TC
C
TC
8
SV00308
LOGIC SYMBOL (IEEE/IEC)
CTR14
3
9
10
11
12
CT
CT = 0
9
11
CX
RX
RCX
!G
+
7
5
4
6
14
13
15
1
2
13
(a)
3
11
12
&
CTR14
3
7
5
4
6
+
CT
CT = 0
9
11
14
13
15
1
2
13
(b)
3
SV00311
1998 Jun 23
3
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74LV4060
DYNAMIC POWER DISSIPATION
GND = 0 V; T
amb
= 25
_C
PARAMETER
Total dynamic power dissipation when
using the on–chip oscillator (P
D
)
V
CC
(V)
1.2
2.0
3.0
TYPICAL FORMULA FOR P
D
(mW)
1
C
PD
x f
osc
x V
CC2
+
S
(C
L
x V
CC2
x f
o
) + 2C
t
x V
CC2
x f
osc
+ 16 x V
CC
C
PD
x f
osc
x V
CC2
+
S
(C
L
x V
CC2
x f
o
) + 2C
t
x V
CC2
x f
osc
+ 460 x V
CC
C
PD
x f
osc
x V
CC2
+
S
(C
L
x V
CC2
x f
o
) + 2C
t
x V
CC2
x f
osc
+ 1000 x V
CC
NOTE:
1. Where: f
o
= output frequency in MHz; f
osc
= oscillator frequency in MHz;
S
(C
L
x V
CC2
x f
o
) = sum of the outputs; C
L
= output load capacitance in pF;
C
t
= timing capacitance in pF; V
CC
= supply voltage in V.
FUNCTIONAL DIAGRAM
10
R
TC
9
C
TC
11
RS
CP
14-stage binary counter
C
D
12
MR
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
Q
9
Q
11
Q
12
Q
13
7
5
4
6
14
13
15
1
2
3
SV00312
LOGIC DIAGRAM
C
TC
R
TC
RS
CP
Q
C
D
FF1
FF4
FF10
FF12
FF14
MR
Q
3
Q
9
Q
11
Q
13
SV00313
1998 Jun 23
4
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74LV4060
TIMING DIAGRAM
1
RS
2
4
8
16
32
64
128
256
512
1.024
2.048
4.096
8.192
16.384
MR
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q11
Q12
Q13
SV00309
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
,
±I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC output diode current
DC output source or sink current
– standard outputs
DC V
CC
or GND current for types with
–standard outputs
Storage temperature range
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
< –0.5 or V
I
> V
CC
+ 0.5V
V
O
< –0.5 or V
O
> V
CC
+ 0.5V
–0.5V < V
O
< V
CC
+ 0.5V
CONDITIONS
RATING
–0.5 to +7.0
20
50
25
50
–65 to +150
750
500
400
UNIT
V
mA
mA
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 23
5
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