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74LV4060-Q100
14-stage binary ripple counter with oscillator
Rev. 1 — 25 July 2014
Product data sheet
1. General description
The 74LV4060-Q100 is a low-voltage Si-gate CMOS device and is pin and function
compatible with the 74HC4060-Q100; 74HCT4060-Q100.
The 74LV4060-Q100 is a 14-stage ripple-carry counter/divider and oscillator with three
oscillator terminals (RS, RTC and CTC). It has ten buffered outputs (Q3 to Q9 and Q11 to
Q13) and an overriding asynchronous master reset (MR). The oscillator configuration
allows design of either RC or crystal oscillator circuits. The oscillator can be replaced by
an external clock signal at input RS. In this case, keep the oscillator pins (RTC and CTC)
floating.
The counter advances on the negative-going transition of RS. A HIGH-level on MR resets
the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of the other input conditions.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide operating voltage range from 1.0 V to 5.5 V
Optimized for low voltage applications from 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V; T
amb
= 25
C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V; T
amb
= 25
C
All active components on chip
RC or crystal oscillator configuration
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
3. Applications
Control counters
Timers
Frequency dividers
Time-delay circuits
NXP Semiconductors
74LV4060-Q100
14-stage binary ripple counter with oscillator
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV4060D-Q100
40 C
to +125
C
Name
SO16
TSSOP16
Description
plastic small outline package; 16 leads; body width
3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT403-1
Type number
74LV4060PW-Q100
40 C
to +125
C
5. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LV4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
2 of 21
NXP Semiconductors
74LV4060-Q100
14-stage binary ripple counter with oscillator
Fig 3.
Logic diagram
Fig 4.
Functional diagram
6. Pinning information
6.1 Pinning
Fig 5.
Pin configuration
74LV4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
3 of 21
NXP Semiconductors
74LV4060-Q100
14-stage binary ripple counter with oscillator
6.2 Pin description
Table 2.
Symbol
Q11 to Q13
Q3 to Q9
GND
CTC
RTC
RS
MR
V
CC
Pin description
Pin
1, 2, 3
7, 5, 4, 6, 14, 13, 15
8
9
10
11
12
16
Description
counter output
counter output
ground (0 V)
external capacitor connection
external resistor connection
clock input/oscillator pin
master reset
supply voltage
7. Functional description
Fig 6.
Timing diagram
74LV4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 25 July 2014
4 of 21
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