74LV132
Quad 2-input NAND Schmitt trigger
Rev. 05 — 2 July 2009
Product data sheet
1. General description
The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC132 and 74HCT132.
The 74LV132 contains four 2-input NAND gates which accept standard input signals.
They are capable of transforming slowly changing input signals into sharply defined,
jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The
difference between the positive voltage V
T+
and the negative voltage V
T−
is defined as the
input hysteresis voltage V
H
.
2. Features
I
I
I
I
I
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
°C
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Applications
I
Wave and pulse shapers for highly noisy environments
I
Astable multivibrators
I
Monostable multivibrators
NXP Semiconductors
74LV132
Quad 2-input NAND Schmitt trigger
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV132N
74LV132D
74LV132DB
74LV132PW
74LV132BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP14
SO14
SSOP14
TSSOP14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
5. Functional diagram
1A
1Y
2
1B
1
2
4
2A
2Y
5
2B
6
4
5
9
3Y
10
3B
10
8
12
13
12
4A
mna408
1
3
&
3
&
6
9
3A
&
8
&
11
A
Y
B
mna409
4Y
13
4B
11
mna407
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
74LV132_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 2 July 2009
2 of 17
NXP Semiconductors
74LV132
Quad 2-input NAND Schmitt trigger
6. Pinning information
6.1 Pinning
74LV132
terminal 1
index area
1B
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
001aac203
2
3
4
5
6
7
GND
3Y
8
V
CC(1)
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
3A
14 V
CC
13 4B
12 4A
1Y
2A
2B
2Y
132
11 4Y
10 3B
9
8
3A
3Y
1
1A
001aah099
Transparent top view
(1) The die substrate is attached to the exposed die pad
using conductive die attach material. It cannot be
used as a supply pin or input.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
Fig 5. Pin configuration DHVQFN14
6.2 Pin description
Table 2.
Symbol
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
74LV132_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 2 July 2009
3 of 17
NXP Semiconductors
74LV132
Quad 2-input NAND Schmitt trigger
7. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level.
Input
nA
L
L
H
H
nB
L
H
L
H
Output
nY
H
H
H
L
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP14 package
SO14 package
(T)SSOP14 package
DHVQFN14 package
[1]
[2]
[3]
[4]
[5]
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Min
−0.5
-
-
-
-
−50
−65
Max
+7.0
±20
±50
±25
50
-
+150
750
500
500
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
mW
mW
mW
T
amb
=
−40 °C
to +125
°C
[2]
[3]
[4]
[5]
-
-
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 12 mW/K above 70
°C.
P
tot
derates linearly with 8 mW/K above 70
°C.
P
tot
derates linearly with 5.5 mW/K above 60
°C.
P
tot
derates linearly with 4.5 mW/K above 60
°C.
74LV132_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 2 July 2009
4 of 17
NXP Semiconductors
74LV132
Quad 2-input NAND Schmitt trigger
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
[1]
Parameter
supply voltage
[1]
input voltage
output voltage
ambient temperature
Conditions
Min
1.0
0
0
−40
Typ
3.3
-
-
+25
Max
5.5
V
CC
V
CC
+125
Unit
V
V
V
°C
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
10. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
OH
HIGH-level output voltage
Conditions
V
I
= V
T+
or V
T−
l
O
=
−100 µA;
V
CC
= 1.2 V
l
O
=
−100 µA;
V
CC
= 2.0 V
l
O
=
−100 µA;
V
CC
= 2.7 V
l
O
=
−100 µA;
V
CC
= 3.0 V
l
O
=
−100 µA;
V
CC
= 4.5 V
l
O
=
−6
mA; V
CC
= 3.0 V
l
O
=
−12
mA; V
CC
= 4.5 V
V
OL
LOW-level output voltage
V
I
= V
T+
or V
T−
I
O
= 100
µA;
V
CC
= 1.2 V
I
O
= 100
µA;
V
CC
= 2.0 V
I
O
= 100
µA;
V
CC
= 2.7 V
I
O
= 100
µA;
V
CC
= 3.0 V
I
O
= 100
µA;
V
CC
= 4.5 V
I
O
= 6 mA; V
CC
= 3.0 V
I
O
= 12 mA; V
CC
= 4.5 V
I
I
I
CC
∆I
CC
C
I
[1]
−40 °C
to +85
°C
Min
-
1.8
2.5
2.8
4.3
2.4
3.6
-
-
-
-
-
-
-
-
-
-
-
Typ
[1]
1.2
2.0
2.7
3.0
4.5
2.82
4.2
0
0
0
0
0
0.25
0.35
-
-
-
3.5
Max
-
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.40
0.55
1.0
20.0
500
-
−40 °C
to +125
°C
Unit
Min
-
1.8
2.5
2.8
4.3
2.2
3.5
-
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.50
0.65
1.0
40
850
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
pF
input leakage current
supply current
additional supply current
input capacitance
V
I
= V
CC
or GND;
V
CC
= 5.5 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
per input; V
I
= V
CC
−
0.6 V;
V
CC
= 2.7 V to 3.6 V
Typical values are measured at T
amb
= 25
°C.
74LV132_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 2 July 2009
5 of 17
NXP MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
