74HC4040; 74HCT4040
12-stage binary ripple counter
Rev. 4 — 20 March 2014
Product data sheet
1. General description
The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP),
an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to
Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of the state of CP. Each
counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC4040: CMOS level
For 74HCT4040: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4040N
74HCT4040N
74HC4040D
74HCT4040D
74HC4040DB
74HCT4040DB
40 C
to +125
C
SSOP16
40 C
to +125
C
SO16
40 C
to +125
C
Name
DIP16
Description
plastic dual in-line package; 16 leads (300 mil);
long body
plastic small outline package; 16 leads; body
width 3.9 mm
Version
SOT38-1
SOT109-1
Type number
plastic shrink small outline package; 16 leads; body SOT338-1
width 5.3 mm
NXP Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 1.
Ordering information
…continued
Package
Temperature range
Name
TSSOP16
Description
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT403-1
40 C
to +125
C
40 C
to +125
C
Type number
74HC4040PW
74HCT4040PW
74HC4040BQ
74HCT4040BQ
DHVQFN16 plastic dual in-line compatible thermal enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
5. Functional diagram
CP
MR
10
11
T
12-STAGE COUNTER
C
D
9
7
6
5
3
2
4
13
12
14
15
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11
001aad589
Fig 1.
Functional diagram
CTR12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
9
7
6
5
3
2
4
13
12
14
15
1
10
11
+
CT = 0
0
9
7
6
5
3
2
4
13
12
14
15
1
10
CP
CT
11
MR
11
001aad585
001aad586
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC_HCT4040
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 20 March 2014
2 of 20
NXP Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
CP
FF
T 1
Q
FF
T 2
Q
FF
T 3
Q
FF
T 4
Q
FF
T 5
Q
FF
T 6
Q
Q
RD
MR
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
Q0
Q1
Q2
Q3
Q4
Q5
FF
T 7
Q
FF
T 8
Q
FF
T 9
Q
FF
T 10
Q
FF
T 11
Q
FF
T 12
Q
Q
RD
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
Q6
Q7
Q8
Q9
Q10
Q11
001aad588
Fig 4.
Logic diagram
6. Pinning information
6.1 Pinning
terminal 1
index area
Q5
Q11
Q5
Q4
Q6
Q3
Q2
Q1
GND
1
2
3
4
5
6
7
8
001aad583
2
3
4
5
6
7
8
GND
Q0
9
16 V
CC
15 Q10
14 Q9
13 Q7
12 Q8
11 MR
10 CP
16 V
CC
15 Q10
14 Q9
13 Q7
12 Q8
11 MR
10 CP
9
Q0
Q4
Q6
Q3
Q2
Q1
4040
GND
(1)
1
Q11
4040
001aad584
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration DIP16, SO16, SSOP16 and
TSSOP16
Fig 6.
Pin configuration DHVQFN16
74HC_HCT4040
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 20 March 2014
3 of 20
NXP Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
6.2 Pin description
Table 2.
Symbol
Q11
Q5
Q4
Q6
Q3
Q2
Q1
GND
Q0
CP
MR
Q8
Q7
Q9
Q10
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
output 11
output 5
output 4
output 6
output 3
output 2
output 1
ground (0 V)
output 0
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
output 8
output 7
output 9
output 10
positive supply voltage
7. Functional description
7.1 Function table
Table 3.
Input
CP
X
[1]
Function table
Output
MR
L
L
H
Q0 to Q11
no change
count
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW-to-HIGH clock transition;
= HIGH-to-LOW clock transition.
74HC_HCT4040
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 20 March 2014
4 of 20
NXP Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
7.2 Timing diagram
1
CP input
MR input
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
001aad587
2
4
8
16
32
64
128
256
512 1024 2048 4096
Fig 7.
Timing diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP16 package
SO16, SSOP16, TSSOP16 and
DHVQFN16 packages
[1]
For DIP16 packages: above 70
C,
P
tot
derates linearly with 12 mW/K.
For SO16, SSOP16, TSSOP16 and DHVQFN16 packages, above 70
C,
P
tot
derates linearly with 8 mW/K.
Conditions
V
I
<
0.5
V or VI > V
CC
+ 0.5 V
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
-
65
Max
+7
20
20
25
50
50
+150
750
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
T
amb
=
40 C
to +125
C
[1]
-
-
74HC_HCT4040
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 20 March 2014
5 of 20
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