74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
Rev. 1 — 12 July 2013
Product data sheet
1. General description
The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter.
Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs
change state synchronously with the LOW-to-HIGH transition of either clock input. If the
CPU clock is pulsed while CPD is held HIGH, the device counts up. If the CPD clock is
pulsed while CPU is held HIGH, the device counts down. Only one clock input can be held
HIGH at any time to guarantee predictable behavior. The device can be cleared at any
time by the asynchronous master reset input (MR). It may also be loaded in parallel by
activating the asynchronous parallel load input (PL). The terminal count up (TCU) and
terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the
maximum count state of 15, the next HIGH-to-LOW transition of CPU causes TCU to go
LOW. TCU remains LOW until CPU goes HIGH again, duplicating the count up clock.
Likewise, the TCD output goes LOW when the circuit is in the zero state and the CPD
goes LOW. The terminal count outputs duplicate the clock waveforms and can be used as
the clock input signals to the next higher-order circuit in a multistage counter. Multistage
counters are not fully synchronous, since there is a slight delay time difference added for
each stage that is added. The counter may be preset by the asynchronous parallel load
capability of the circuit. Information on the parallel data inputs (D0 to D3), is loaded into
the counter. This information appears on the outputs (Q0 to Q3) regardless of the
conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on
the master reset (MR) input disables the parallel load gates. It overrides both clock inputs
and sets all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of that clock is interpreted as a
legitimate signal and it is counted. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Input levels:
For 74HC193-Q100: CMOS level
For 74HCT193-Q100: TTL level
Synchronous reversible 4-bit binary counting
Asynchronous parallel load
Asynchronous reset
Expandable without external logic
Complies with JEDEC standard no. 7A
NXP Semiconductors
74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74HC193D-Q100
74HC193DB-Q100
74HC193PW-Q100
74HCT193D-Q100
74HCT193DB-Q100
74HCT193PW-Q100
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO16
SSOP16
TSSOP16
SO16
SSOP16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT109-1
SOT338-1
SOT403-1
Type number
4. Functional diagram
15
D0
1
D1
10
D2
9
D3
TCU
COUNTER
TCD
12
13
CPU
14
MR
FLIP-FLOPS
Q0
3
2
Q1
6
Q2
7
Q3
001aag405
11
5
4
PL
CPU
CPD
PL
11
5
4
14
MR
D0
15
D1
1
D2
10
D3
9
12
13
TCU
TCD
CPD
3
Q0
2
Q1
6
Q2
7
Q3
001aag409
Fig 1. Functional diagram
Fig 2. Logic symbol
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 12 July 2013
2 of 29
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Product data sheet
Rev. 1 — 12 July 2013
4 of 29
74HC_HCT139_Q100
NXP Semiconductors
D0
D1
D2
D3
PL
CPU
TCU
All information provided in this document is subject to legal disclaimers.
74HC193-Q100; 74HCT193-Q100
SD
T
Q
T
SD
Q
T
SD
Q
T
SD
Q
Presettable synchronous 4-bit binary up/down counter
FF1
Q
RD
FF2
Q
RD
FF3
Q
RD
FF4
Q
RD
TCD
CPD
MR
Q0
Q1
Q2
Q3
001aag412
© NXP B.V. 2013. All rights reserved.
Fig 4. Logic diagram
NXP Semiconductors
74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1 Pinning
Fig 5. Pin configuration SO16
Fig 6. Pin configuration TSSOP16 and SSOP16
5.2 Pin description
Table 2.
Symbol
D0
D1
D2
D3
Q0
Q1
Q2
Q3
CPD
CPU
GND
PL
TCU
TCD
MR
V
CC
[1]
Pin description
Pin
15
1
10
9
3
2
6
7
4
5
8
11
12
13
14
16
Description
data input 0
data input 1
data input 2
data input 3
flip-flop output 0
flip-flop output 1
flip-flop output 2
flip-flop output 3
count down clock input
[1]
count up clock input
[1]
ground (0 V)
asynchronous parallel load input (active LOW)
terminal count up (carry) output (active LOW)
terminal count down (borrow) output (active LOW)
asynchronous master reset input (active HIGH)
supply voltage
LOW-to-HIGH, edge triggered.
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 12 July 2013
5 of 29
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