74HC163-Q100; 74HCT163-Q100
Presettable synchronous 4-bit binary counter; synchronous
reset
Rev. 1 — 19 June 2014
Product data sheet
1. General description
The 74HC163-Q100; 74HCT163-Q100 is a synchronous presettable binary counter with
an internal look-head carry. Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to
Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input
(PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be
loaded into the counter on the positive-going edge of the clock. Preset takes place
regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset
input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input
(CP). This action occurs regardless of the levels at input pins PE, CET and CEP. This
synchronous reset feature enables the designer to modify the maximum count with only
one external NAND gate. The look-ahead carry simplifies serial cascading of the counters.
Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the
terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse
of a duration approximately equal to a HIGH output of Q0. This pulse can be used to
enable the next cascaded stage. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of V
CC
.
The CP to TC propagation delay and CEP to CP set-up time determine the maximum
clock frequency for the cascaded counters according to the following formula:
1
f
max
=
---------------------------------------------------------------------------------------
-
t
P
max
CPtoTC
+
t
SU
CEPtoCP
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Complies with JEDEC standard no. 7A
Input levels:
For 74HC163-Q100: CMOS level
For 74HCT163-Q100: TTL level
Synchronous counting and loading
2 count enable inputs for n-bit cascading
Synchronous reset
Positive-edge triggered clock
NXP Semiconductors
74HC163-Q100; 74HCT163-Q100
Presettable synchronous 4-bit binary counter; synchronous reset
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74HC163D-Q100
74HCT163D-Q100
74HC163PW-Q100
74HCT163PW-Q100
40 C
to +125
C
TSSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT109-1
Type number
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
74HC_HCT163_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
2 of 23
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Product data sheet
Rev. 1 — 19 June 2014
4 of 23
74HC_HCT163_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
NXP Semiconductors
Presettable synchronous 4-bit binary counter; synchronous reset
74HC163-Q100; 74HCT163-Q100
Fig 4.
Logic diagram
NXP Semiconductors
74HC163-Q100; 74HCT163-Q100
Presettable synchronous 4-bit binary counter; synchronous reset
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SO16
Fig 6.
Pin configuration TSSOP16
5.2 Pin description
Table 2.
Symbol
MR
CP
D0, D1, D2, D3
CEP
GND
PE
CET
Q0, Q1, Q2, Q3
TC
V
CC
Pin description
Pin
1
2
3, 4, 5, 6
7
8
9
10
14, 13, 12, 11
15
16
Description
synchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge triggered)
data input
count enable input
ground (0 V)
parallel enable input (active LOW)
count enable carry input
flip-flop output
terminal count output
supply voltage
74HC_HCT163_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
5 of 23
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