74HC161-Q100
Rev. 2 — 4 October 2018
Presettable synchronous 4-bit binary counter; asynchronous
reset
Product data sheet
1. General description
The 74HC161-Q100 is a synchronous presettable binary counter with an internal look-head carry.
Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-
going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW.
A LOW at the parallel enable input (PE) disables the counting action and causes the data at the
data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset
takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master
reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP
(thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading
of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a
duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next
cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP
to TC propagation delay and CEP to CP set-up time, according to the following formula:
Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to
voltages in excess of V
CC
.
2. Features and benefits
•
•
•
•
•
•
•
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
•
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Complies with JEDEC standard no. 7A
CMOS input levels
Synchronous counting and loading
2 count enable inputs for n-bit cascading
Asynchronous reset
Positive-edge triggered clock
ESD protection:
•
MIL-STD-883, method 3015 exceeds 2000 V
•
HBM JESD22-A114F exceeds 2 000 V
•
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Multiple package options
•
Nexperia
74HC161-Q100
Presettable synchronous 4-bit binary counter; asynchronous reset
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC161D-Q100
-40 °C to +125 °C
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT109-1
SOT403-1
74HC161PW-Q100 -40 °C to +125 °C
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
4. Functional diagram
1
15
TC
3
4
5
6
9
D0
D1
D2
D3
PE
CEP CET
7
10
CP
2
MR
1
mna905
Q0
Q1
Q2
Q3
14
13
12
11
9
7
10
2
3
4
5
6
R
M1
G3
G4
CTR4
C2/1,3,4+
1,2D
14
13
12
11
4 CT = 15
mna906
15
Fig. 1.
Logic symbol
3
D0
9
10
7
2
1
PE
CET
CEP
CP
MR
4
Fig. 2.
5
D1
D2
6
D3
IEC logic symbol
PARALLEL LOAD
CIRCUITRY
TC
BINARY
COUNTER
15
Q0
14
Q1
13
Q2
12
Q3
11
mna907
Fig. 3.
Functional diagram
74HC161_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 2 — 4 October 2018
2 / 17
Nexperia
74HC161-Q100
Presettable synchronous 4-bit binary counter; asynchronous reset
D0
D1
D2
D3
CET
CEP
PE
D
FF0
Q
D
FF1
Q
Q
D
FF2
Q
Q
D
FF3
Q
Q
CP
CP
Q
CP
CP
R
D
CP
MR
R
D
R
D
R
D
Q0
Q1
Q2
Q3
TC
mna910
Fig. 4.
Logic diagram
74HC161_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 2 — 4 October 2018
3 / 17
Nexperia
74HC161-Q100
Presettable synchronous 4-bit binary counter; asynchronous reset
5. Pinning information
5.1. Pinning
74HC161
MR
CP
D0
D1
D2
D3
CEP
GND
1
2
3
4
5
6
7
8
aaa-024396
16 V
CC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
9
PE
MR
CP
D0
D1
D2
D3
CEP
GND
1
2
3
4
5
6
7
8
aaa-024397
74HC161
16 V
CC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
9
PE
Fig. 5.
Pin configuration SOT109-1 (SO16)
Fig. 6.
Pin configuration SOT403-1 (TSSOP16)
5.2. Pin description
Table 2. Pin description
Symbol
MR
CP
D0, D1, D2, D3
CEP
GND
PE
CET
Q0, Q1, Q2, Q3
TC
V
CC
Pin
1
2
3, 4, 5, 6
7
8
9
10
14, 13, 12, 11
15
16
Description
asynchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
count enable input
ground (0 V)
parallel enable input (active LOW)
count enable carry input
flip-flop output
terminal count output
supply voltage
74HC161_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 2 — 4 October 2018
4 / 17
Nexperia
74HC161-Q100
Presettable synchronous 4-bit binary counter; asynchronous reset
6. Functional description
Table 3. Function table[1]
Operating
Input
modes
MR
CP
Reset (clear) L
Parallel load
Count
Hold
(do nothing)
[1]
Output
CEP
X
X
X
h
l
X
CET
X
X
X
h
X
l
PE
X
l
l
h
h
h
Dn
X
l
h
X
X
X
Qn
L
L
H
count
q
n
q
n
TC
L
L
[2]
[2]
[2]
L
X
↑
↑
↑
X
X
H
H
H
H
H
[2]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q
n
= lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition
X = don’t care
↑ = LOW-to-HIGH clock transition
The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH)
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
aaa-012187
Fig. 7.
State diagram
74HC161_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 2 — 4 October 2018
5 / 17
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