Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
HF
IR
SI
D
0
D
1
D
2
D
3
D
4
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Vcc
AF/E
SO
OR
Q
0
Q
1
Q
2
Q
3
Q
4
MR
2748 drw 02
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage with
Respect to GND
Storage
Temperature
DC Output
Current
Commercial
–0.5 to +7.0
–55 to +125
–50 to +50
Unit
V
°C
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
PLASTIC DIP (P20-1, ORDER CODE: P)
SOIC (SO20-2, ORDER CODE: SO)
TOP VIEW
RECOMMENDED OPERATING
CONDITIONS
Symbol
V
CC
Parameter
Supply Voltage
Commercial
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Commercial
Min.
4.5
0
2.0
—
0
Typ.
5.0
0
—
—
—
Max.
5.5
0
—
0.8
70
Unit
V
V
V
V
°C
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
5
7
Unit
pF
pF
2748 tbl 02
GND
V
IH
V
IL
T
A
(1)
NOTE:
1. Characterized values, not currently tested.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V ± 10%, T
A
= 0°C to +70°C)
IDT72413
Commercial
f
IN
= 45, 35, 25 MHz
Max.
—
10
0.4
Symbol
I
IL
IIH
V
OL
Parameter
Low-Level Input Current
High-Level Input Current
Low-Level Output Current
V
OH
High-Level Output Current
I
OS (2)
I
HZ
I
LZ
I
CC(3,4)
Output Short-Circuit Current
HIGH Impedance Output Current
LOW Impedance Output Current
Active Supply Current
Test Conditions
V
CC
= Max., GND
≤
V
I
≤
V
CC
V
CC
= Max., GND
≤
V
I
≤
V
CC
V
CC
= Min. I
OL
(Q
0-4
)
I
OL
(IR, OR)
(1)
I
OL
(HF, AF/E)
V
CC
= Min. I
OH
(Q
0-4
)
I
OH
(IR, OR)
I
OH
(HF, AF/E)
V
CC
= Max. V
O
= 0V
V
CC
= Max. V
O
= 2.4V
V
CC
= Max. V
O
= 0.4V
V
CC
= Max.,
OE
= HIGH
Inputs LOW, f = 25MHz
24 mA
8mA
8mA
–4mA
–4mA
–4mA
Min.
–10
—
—
Unit
μ
A
μA
V
2.4
—
V
–20
—
–20
—
–110
20
—
60
mA
μ
A
μ
A
mA
NOTES:
1. Care should be taken to minimize as much as possible the DC and capactive load on IR and OR when operating at frequencies above 25MHz.
2. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Guaranteed by design, but not currently tested.
3. Tested with outputs open (I
OUT
= 0).
4. For frequencies greater than 25MHz, I
CC
= 60mA + (1.5mA x [f –25MHz])
2
JUNE 29, 2012
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5
COMMERCIAL TEMPERATURE RANGE
OPERATING CONDITIONS
(Commercial: V
CC
= 5.0V ± 10%, T
A
= 0°C to +70°C)
IDT72413L45
Min.
Max.
9
—
11
—
0
—
13
—
9
—
11
—
20
—
20
—
Commercial
IDT72413L35
Min.
Max.
9
—
17
—
0
—
15
—
9
—
17
—
30
—
35
—
IDT72413L25
Min.
Max.
16
—
20
—
0
—
25
—
16
—
20
—
35
—
35
—
Symbol
t
SIH(1)
t
SIL(1)
t
IDS
t
IDH
t
SOH(1)
t
SOL
t
MRW
t
MRS
Parameter
Shift in HIGH Time
Shift in LOW TIme
Input Data Set-up
Input Data Hold Time
Shift Out HIGH Time
Shift Out LOW Time
Master Reset Pulse
Master Reset Pulse to SI
Figure
2
2
2
2
5
5
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NOTE:
1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling
are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding.
A monolithic ceramic capacitor of 0.1μF directly between VCC and GND with very short lead length is recommended.
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V ± 10%, T
A
= 0°C to +70°C)
Commercial
Symbol
f
IN
t
IRL(1)
t
IRH(1)
f
OUT
t
ORL(1)
t
ORH(1)
t
ODH(1)
t
ODS
t
PT
t
MRORL
t
MRIRH(3)
t
MRIRL(2)
t
MRQ
t
MRHF
t
MRAFE
t
IPH(3)
t
OPH(3)
t
ORD(3)
t
AEH
t
AEL
t
AFL
t
AFH
t
HFH
t
HFL
t
PHZ(3)
t
PLZ (3)
t
PLZ (3)
t
PHZ(3)
Parameter
Shift In Rate
Shift In
↑
to Input Ready LOW
Shift In
↓
to Input Ready HIGH
Shift Out Rate
Shift Out
↓
to Output Ready LOW
Shift Out
↓
to Output Ready HIGH
Output Data Hold Previous Word
Output Data Shift Next Word
Data Throughput or "Fall-Through"
Master Reset
↓
to Output Ready LOW
Master Reset
↑
to Input Ready HIGH
Master Reset
↓
to Input Ready LOW
Master Reset
↓
to Outputs LOW
Master Reset
↓
to Half-Full Flag
Master Reset
↓
to AF/E Flag
Input Ready Pulse HIGH
Output Ready Pulse HIGH
Output Ready
↑
HIGH to Valid Data
Shift Out
↑
to AF/E HIGH
Shift In
↑
to AF/E
Shift Out
↑
to AF/E LOW
Shift In
↑
to AF/E HIGH
Shift In
↑
to HF HIGH
Shift Out
↑
to HF LOW
Output Disable Delay
Output Enable Delay
Figure
2
2
2
5
5
5
5
5
4, 7
8
8
8
8
8
8
4
7
5
9
9
10
10
11
11
12
12
12
12
IDT72413L45
Min.
Max.
—
45
—
18
—
18
—
45
—
18
—
19
5
—
—
19
—
25
—
25
—
25
—
25
—
20
—
25
—
25
5
—
5
—
—
5
—
28
—
28
—
28
—
28
—
28
—
28
—
12
—
12
—
15
—
15
IDT72413L35
Min.
Max.
—
35
—
18
—
20
—
35
—
18
—
20
5
—
—
20
—
28
—
28
—
28
—
28
—
25
—
28
—
28
5
—
5
—
—
5
—
28
—
28
—
28
—
28
—
28
—
28
—
12
—
12
—
15
—
15
IDT72413L25
Min.
Max.
—
25
—
28
—
25
—
25
—
28
—
25
5
—
—
20
—
40
—
30
—
30
—
30
—
35
—
40
—
40
5
—
5
—
—
7
—
40
—
40
—
40
—
40
—
40
—
40
—
15
—
15
—
20
—
20
Unit
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Since the FIFO is a very high-speed device, care must be taken in the design of the hardware and the timing utilized within the design. Device grounding and decoupling
are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding.
A monolithic ceramic capacitor of 0.1μF directly between V
CC
and GND with very short lead length is recommended.
2. If the FIFO is full, (IR = HIGH),
MR
↑
forces IR to go LOW, and
MR
↓
causes IR to go HIGH.
3. Guaranteed by design but not currently tested.
3
JUNE 29, 2012
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5
COMMERCIAL TEMPERATURE RANGE
STANDARD TEST LOAD
DESIGN TEST LOAD
5V
R1
OUTPUT
2748 tbl 07
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
5V
2K‰
TEST POINT
30pF*
30pF*
R2
or equivalent circuit
*Including scope and jig
2748 drw 03
RESISTOR VALUES FOR
STANDARD TEST LOAD
I
OL
24mA
12mA
8mA
R1
200Ω
390Ω
600Ω
R2
300Ω
760Ω
1200Ω
Figure 1. Output Load
FUNCTIONAL DESCRIPTION:
The IDT72413, 65 x 5 FIFO is designed using a dual-port RAM architecture
as opposed to the traditional shift register approach. This FIFO architecture has
a write pointer, a read pointer and control logic, which allow simultaneous read
and write operations. The write pointer is incremented by the falling edge of the
Shift In (Sl) control; the read pointer is incremented by the falling edge of the Shift
Out (SO). The Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is valid data on the
output. Output Enable (OE) provides the capability of three-stating the FIFO
outputs.
FIFO RESET
The FIFO must be reset upon power up using the Master Reset (MR) signal.
This causes the FIFO to enter an empty state signified by Output Ready (OR)
being LOW and Input Ready (IR) being HIGH. In this state, the data outputs
(Q
0
-
4
) will be LOW.
DATA INPUT
Data is shifted in on the LOW-to-HIGH transition of Shift In (Sl). This loads
input data into the first word location of the FIFO and causes the lnput Ready
(IR) to go LOW. On the HlGH-to-LOW transition of SI, the write pointer is moved
to the next word position and lR goes HlGH indicating the readiness to accept
new data. If the FIFO is full, IR will remain LOW until a word of data is shifted
out.
DATA OUTPUT
Data is shifted out on the HIGH-to-LOW transition of Shift Out (SO). This causes
the internal read pointer to be advanced to the next word location. If data is
present, valid data will appear on the outputs and Output Ready (OR) will go
HIGH. If data is not present, OR will stay LOW indicating the FIFO is empty. The
last valid word read from the FIFO will remain at the FlFOs output when it is empty.
When the FIFO is not empty OR goes LOW on the LOW-to-HlGH transition of
SO.
FALL-THROUGH MODE
The FIFO operates in a Fall-Through Mode when data gets shifted into an
empty FIFO. After the fall-through delay the data propagates to the output. When
the data reaches the output, the Output Ready (OR) goes HIGH.
A Fall-Through Mode also occurs when the FIFO is completely full. When
data is shifted out of the full FIFO a location is available for new data. After a fall-
through delay, the lnput Ready goes HlGH. If Shift In is HIGH, the new data
can be written to the FIFO. The fall-through delay of a RAM-based FIFO (one
clock cycle) is far less than the delay of a Shift register-based FIFO.
SIGNAL DESCRIPTIONS:
INPUTS:
DATA INPUT (D
0
-
4
)
Data input lines. The IDT72413 has a 5-bit data input.
4
JUNE 29, 2012
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5
COMMERCIAL TEMPERATURE RANGE
CONTROLS:
SHIFT IN (SI)
Shift In controls the input of the data into the FIFO. When SI is HIGH, data
can be written to the FIFO via the D0-4 lines. The data has to meet set-up and
hold time requirements with respect to the rising edge of SI.
SHIFT OUT (SO)
Shift Out controls the outputs data from the FIFO.
MASTER RESET (MR)
Master Reset clears the FIFO of any data stored within. Upon power up, the
FIFO should be cleared with a Master Reset. Master Reset is active LOW.
HALF-FULL FLAG (HF)
Half-Full Flag signals when the FIFO has 32 or more words in it.
INPUT READY (IR)
When Input Ready is HIGH, the FIFO is ready for new input data to be written
to it. When IR is LOW, the FIFO is unavailable for new input data, IR is also
used to cascade many FIFOs together, as shown in Figure 13.
OUTPUT READY (OR)
When Output Ready is HIGH, the output (Q
0
-
4
) contains valid data. When
OR is LOW, the FIFO is unavailable for new output data. OR is also used to
cascade many FIFOs together, as shown in Figure 13.
OUTPUT ENABLE (OE)
Output Enable is used to enable the FIFO outputs onto a bus.
OE
is active
LOW.
ALMOST-FULL/EMPTY FLAG (AF/E)
Almost-Full/Empty Flag signals when the FIFO is 7/8 full (56 or more words)
or 1/8 from empty (8 or less words).
OUTPUTS:
DATA OUTPUT (Q
0
-
4
)
Data output lines, three-state. The IDT72413 has a 5-bit output.
1/f
IN
t
SIH
SI
t
SIL
1/f
IN
t
IRH
IR
t
IDS
INPUT DATA
2748 drw 04
t
IDH
t
IRL
Figure 2. Input Timing
SI
(7)
(2)
(4)
(1)
IR
(3)
(5)
(6)
INPUT DATA
STABLE DATA
2748 drw 05
NOTES:
1. IR HIGH indicates space is available and a SI pulse may be applied.
2. Input Data is loaded into the FIFO.
3. IR goes LOW indicating the FIFO is unavailable for new data.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full, then IR remains LOW.
7. SI pulses applied while IR is LOW will be ignored (see Figure 4).
Figure 3. The Machanism of Shifting Data Into the FIFO
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
