without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
07/15/03
1
IS93C56A
IS93C66A
ISSI
8-Pin JEDEC SOIC “G”
8-Pin JEDEC SOIC “GR”
ORG
GND
D
OUT
D
IN
®
PIN CONFIGURATIONS
8-Pin DIP, 8-Pin TSSOP
CS
SK
D
IN
D
OUT
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
NC
VCC
CS
SK
1
2
3
4
8
7
6
5
CS
SK
D
IN
D
OUT
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
(Rotated)
PIN DESCRIPTIONS
CS
SK
D
IN
D
OUT
ORG
NC
Vcc
GND
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Organization Select
Not Connected
Power
Ground
instruction begins with a start bit of the logical “1” or
HIGH. Following this are the opcode (2 bits),
address field (8 or 9 bits), and data, if appropriate. The
clock signal may be held stable at any moment to
suspend the device at its last state, allowing clock-
speed flexibility. Upon completion of bus
communication, CS would be pulled LOW. The device
then would enter Standby mode if no internal
programming is underway.
Read (READ)
The READ instruction is the only instruction that outputs
serial data on the D
OUT
pin. After the read instruction and
address have been decoded, data is transferred from the
selected memory register into a serial shift register. (Please
note that one logical “0” bit precedes the actual 8 or 16-bit
output data string.) The output on D
OUT
changes during the
low-to-high transitions of SK (see Figure 3).
Applications
The IS93C56A/66A are very popular in many
applications which require low-power, low-density
storage. Applications using these devices include
industrial controls, networking, and numerous other
consumer electronics.
Low Voltage Read
The IS93C56A/66A are designed to ensure that data read
operations are reliable in low voltage environments. They
provide accurate operation with Vcc as low as 1.8V.
Endurance and Data Retention
The IS93C56A/66A are designed for applications requiring
up to 1M programming cycles (WRITE, WRALL, ERASE
and ERAL). They provide 40 years of secure data retention
without power after the execution of 1M programming cycles.
Auto Increment Read Operations
In the interest of memory transfer operation applications,
the IS93C56A/66A are designed to output a continuous
stream of memory content in response to a single read
operation instruction. To utilize this function, the system
asserts a read instruction specifying a start location ad-
dress. Once the 8 or16 bits of the addressed register have
been clocked out, the data in consecutively higher address
locations is output. The address will wrap around continu-
ously with CS HIGH until the chip select (CS) control pin is
brought LOW. This allows for single instruction data dumps
to be executed with a minimum of firmware overhead.
Device Operations
The IS93C56A/66A are controlled by a set of
instructions which are clocked-in serially on the Din pin.
Before each low-to-high transition of the clock (SK), the
CS pin must have already been raised to HIGH, and the
Din value must be stable at either LOW or HIGH. Each
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
07/15/03
IS93C56A
IS93C66A
ISSI
Write All (WRALL)
®
Write Enable (WEN)
The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL,
ERASE, and ERAL) can be done. When Vcc is applied,
this device powers up in the write disabled state. The
device then remains in a write disabled state until a WEN
instruction is executed. Thereafter, the device remains
enabled until a WDS instruction is executed or until Vcc
is removed. (See Figure 4.) (Note: Chip select must
remain LOW until Vcc reaches its operational value.)
The write all (WRALL) instruction programs all registers
with the data pattern specified in the instruction. As with the
WRITE instruction, the falling edge of CS must occur to
initiate the self-timed programming cycle. If CS is then
brought HIGH after a minimum wait of 200 ns (t
CS
), the D
OUT
pin indicates the READY/BUSY status of the chip (see
Figure 6). Vcc is required to be above 4.5V for WRALL to
function properly.
Write Disable (WDS)
The write disable (WDS) instruction disables all programming
capabilities. This protects the entire device against acci-
dental modification of data until a WEN instruction is
executed. (When Vcc is applied, this part powers up in the
write disabled state.) To protect data, a WDS instruction
should be executed upon completion of each programming
operation.
Write (WRITE)
The WRITE instruction includes 8 or 16 bits of data to be
written into the specified register. After the last data bit
has been applied to D
IN
, and before the next rising edge
of SK, CS must be brought LOW. If the device is write-
enabled, then the falling edge of CS initiates the self-
timed programming cycle (see WEN).
If CS is brought HIGH, after a minimum wait of 200 ns (5V
operation) after the falling edge of CS (t
CS
) D
OUT
will
indicate the READY/BUSY status of the chip. Logical “0”
means programming is still in progress; logical “1” means
the selected register has been written, and the part is
ready for another instruction (see Figure 5). The READY/
BUSY
status will not be available if: a) The CS input goes
HIGH after the end of the self-timed programming cycle,
t
WP
; or b) Simultaneously CS is HIGH, Din is HIGH, and
SK goes HIGH, which clears the status flag.
Erase Register (ERASE)
After the erase instruction is entered, CS must be brought
LOW. The falling edge of CS initiates the self-timed internal
programming cycle. Bringing CS HIGH after a minimum of
t
CS
, will cause D
OUT
to indicate the READ/BUSY status of the
chip: a logical “0” indicates programming is still in progress;
a logical “1” indicates the erase cycle is complete and the
part is ready for another instruction (see Figure 8).
Erase All (ERAL)
Full chip erase is provided for ease of programming. Erasing
the entire chip involves setting all bits in the entire memory
array to a logical “1” (see Figure 9). Vcc is required to be
above 4.5V for ERALL to function properly.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
07/15/03
3
IS93C56A
IS93C66A
ISSI
8-bit Organization
(ORG = GND)
Address
(1)
Input Data
x(A
7
-A
0
)
11xxxxxxx
x(A
7
-A
0
)
01xxxxxxx
00xxxxxxx
x(A
7
-A
0
)
10xxxxxxx
—
—
(D
7
-D
0
)
(D
7
-D
0
)
—
—
—
®
INSTRUCTION SET - IS93C56A (2kb)
16-bit Organization
(ORG = Vcc)
Address
(1)
Input Data
x(A
6
-A
0
)
11xxxxxx
x(A
6
-A
0
)
01xxxxxx
00xxxxxx
x(A
6
-A
0
)
10xxxxxx
—
—
(D
15
-D
0
)
(D
15
-D
0
)
—
—
—
Instruction
(2)
READ
WEN
(Write Enable)
WRITE
Start Bit OP Code
1
1
1
1
1
1
1
10
00
01
00
00
11
00
WRALL
(Write All Registers)
WDS
(Write Disable)
ERASE
ERAL (
Erase All Registers)
Notes:
1. x = Don't care bit.
2. If the number of bits clocked-in does not match the number corresponding to a selected command, then all extra trailing bits are
ignored, and WRITE, WRALL, ERASE, and ERAL are also ignored, but READ, WEN, WDS are accepted.
INSTRUCTION SET - IS93C66A (4kb)
8-bit Organization
(ORG = GND)
Address
(1)
Input Data
(A
8
-A
0
)
11xxxxxxx
(A
8
-A
0
)
01xxxxxxx
00xxxxxxx
(A
8
-A
0
)
10xxxxxxx
—
—
(D
7
-D
0
)
(D
7
-D
0
)
—
—
—
16-bit Organization
(ORG = Vcc)
Address
(1)
Input Data
x(A
6
-A
0
)
11xxxxxx
x(A
6
-A
0
)
01xxxxxx
00xxxxxx
x(A
6
-A
0
)
10xxxxxx
—
—
(D
15
-D
0
)
(D
15
-D
0
)
—
—
—
Instruction
(2)
READ
WEN
(Write Enable)
WRITE
Start Bit OP Code
1
1
1
1
1
1
1
10
00
01
00
00
11
00
WRALL
(Write All Registers)
WDS
(Write Disable)
ERASE
ERAL (
Erase All Registers)
Notes:
1. x = Don't care bit.
2. If the number of bits clocked-in does not match the number corresponding to a selected command, then all extra trailing bits are
ignored, and WRITE, WRALL, ERASE, and ERAL are also ignored, but READ, WEN, WDS are accepted.
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
07/15/03
IS93C56A
IS93C66A
ISSI
Value
–0.3 to +6.5
–40 to +85
–40 to +125
–65 to +150
Unit
V
°C
°C
°C
®
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
GND
T
BIAS
T
BIAS
T
STG
Parameter
Voltage with Respect to GND
Temperature Under Bias (Industrial)
Temperature Under Bias (Automotive)
Storage Temperature
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE
Range
Industrial
Automotive
Ambient Temperature
–40°C to +85°C
–40°C to +125°C
V
CC
1.8V to 5.5V or 2.5V to 5.5V
2.5V to 5.5V
CAPACITANCE
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
5
5
Unit
pF
pF
Integrated Silicon Solution, Inc. — www.issi.com —
“tensymetry”这个词在《韦伯斯特词典》中没有解释，但在医学界却广为人知。由Tensys Medical Systems公司开发的tensymetry是一种使用生物机械、电气、软件工程的专有组合技术。利用这三种强大的技术，你可在手术室内对病人的心跳血压进行精确、连续、实时和非侵入性测量。 该技术结出的果实就是该公司的T-line Tensymeter产品。该产品线的最新进展是去年...[详细]
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
