DATASHEET
ISL6594D
Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features
The ISL6594D is high frequency MOSFET driver specifically
designed to drive upper and lower power N-Channel
MOSFETs in a synchronous rectified buck converter
topology. This driver combined with the ISL6594D Digital
Multi-Phase Buck PWM controller and N-Channel MOSFETs
forms a complete core-voltage regulator solution for
advanced microprocessors.
The ISL6594D drives both upper and lower gates over a range
of 4.5V to 13.2V. This drive-voltage provides the flexibility
necessary to optimize applications involving trade-offs between
gate charge and conduction losses.
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. The ISL6594D includes an overvoltage protection
feature operational before VCC exceeds its turn-on
threshold, at which the PHASE node is connected to the
gate of the low side MOSFET (LGATE). The output voltage
of the converter is then limited by the threshold of the low
side MOSFET, which provides some protection to the
microprocessor if the upper MOSFET(s) is shorted.
The ISL6594D also features an input that recognizes a
high-impedance state, working together with Intersil multi-
phase PWM controllers to prevent negative transients on the
controlled output voltage when operation is suspended. This
feature eliminates the need for the Schottky diode that may
be utilized in a power system to protect the load from
negative output voltage damage.
FN9282
Rev 1.00
Dec 3, 2007
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Pin-to-pin Compatible with ISL6596
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- Auto-zero of r
DS(ON)
Conduction Offset Effect
• Adjustable Gate Voltage for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 2MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Optimized for 3.3V PWM Input
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free (RoHS Compliant)
Ordering Information
PART NUMBER
PART
TEMP.
(Note)
MARKING RANGE (°C)
ISL6594DCBZ
6594 DCBZ
0 to +85
0 to +85
0 to +85
0 to +85
PACKAGE
(Pb-free)
8 Ld SOIC
PKG.
DWG. #
M8.15
Applications
• Optimized for POL DC/DC Converters for IBA Systems
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
ISL6594DCBZ-T* 6594 DCBZ
ISL6594DCRZ
94DZ
8 Ld SOIC
M8.15
Tape and Reel
10 Ld 3x3 DFN L10.3x3
10 Ld 3x3 DFN L10.3x3
Tape and Reel
ISL6594DCRZ-T* 94DZ
Related Literature
Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
FN9282 Rev 1.00
Dec 3, 2007
Page 1 of 11
ISL6594D
Pinouts
ISL6594DCB
(8 LD SOIC)
TOP VIEW
UGATE
BOOT
PWM
GND
1
2
3
4
8
7
6
5
PHASE
PVCC
VCC
LGATE
UGATE
BOOT
N/C
PWM
GND
ISL6594DCR
(10 LD 3x3 DFN)
TOP VIEW
1
2
3
4
5
GND
10 PHASE
9 PVCC
8
7
N/C
VCC
6 LGATE
Block Diagram
UVCC
VCC
+5V
13.6k
PWM
POR/
CONTROL
LOGIC
Pre-POR OVP
FEATURES
ISL6594D
BOOT
UGATE
PHASE
(LVCC)
PVCC
UVCC = PVCC FOR ISL6594D
SHOOT-
THROUGH
PROTECTION
6.4k
LGATE
GND
PAD
FOR DFN DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
FN9282 Rev 1.00
Dec 3, 2007
Page 2 of 11
Typical Application - 4 Channel Converter Using ISL6592 and ISL6594D Gate Drivers
+12V
FN9282 Rev 1.00
Dec 3, 2007
Page 3 of 11
ISL6594D
+5V
ISL6594D
1 UGATE
2 BOOT
3 PWM
4 GND
PHASE 8
PVCC 7
VCC 6
LGATE 5
+3.3V
VDD
V12_SEN
GND
ISL6594D
1 UGATE
2 BOOT
3 PWM
4 GND
PHASE 8
PVCC 7
VCC 6
LGATE 5
ISL6592
VID4
VID3
VID2
VID1
FROM µP
VID0
VID5
LL0
LL1
OUTEN
OUT1
OUT2
ISEN1
OUT3
OUT4
ISEN2
OUT5
OUT6
ISEN3
OUT7
OUT8
ISL6594D
1 UGATE
2 BOOT
3 PWM
4 GND
PHASE 8
PVCC 7
VCC 6
LGATE 5
Vout
TO µP
VCC_PWRGD
ISEN4
OUT9
RTN
RESET_N
OUT10
ISEN5
ISL6594D
1 UGATE
2 BOOT
3 PWM
4 GND
PHASE 8
PVCC 7
VCC 6
LGATE 5
FAULT
OUTPUTS
FAULT1
FAULT2
OUT11
OUT12
ISEN6
SDA
I
2
C I/F
BUS
SCL
SADDR
TEMP_SEN
CAL_CUR_EN
CAL_CUR_SEN
VSENP
VSENN
RTHERM
ISL6594D
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (V
BOOT-GND
). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (V
PWM
) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . V
PHASE
- 0.3V
DC
to V
BOOT
+ 0.3V
V
PHASE
- 3.5V (<100ns Pulse Width, 2µJ) to V
BOOT
+ 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
DC
to V
PVCC
+ 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to V
PVCC
+ 0.3V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
DC
to 15V
DC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, V
BOOT-GND
<36V))
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance
JA
(°C/W)
JC
(°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
100
N/A
DFN Package (Notes 2, 3) . . . . . . . . . .
48
7
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to +85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air.
2.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Bias Supply Current
Recommended Operating Conditions, Unless Otherwise Noted.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
VCC
I
VCC
ISL6594D, f
PWM
= 300kHz, V
VCC
= 12V
ISL6594D, f
PWM
= 1MHz, V
VCC
= 12V
ISL6594D, f
PWM
= 300kHz, V
PVCC
= 12V
ISL6594D, f
PWM
= 1MHz, V
PVCC
= 12V
-
-
-
-
4.5
5
7.5
8.5
-
-
-
-
mA
mA
mA
mA
Gate Drive Bias Current
I
PVCC
I
PVCC
POWER-ON RESET AND ENABLE
VCC Rising Threshold
VCC Falling Threshold
PWM INPUT (See Timing Diagram on page 6)
Input Current
I
PWM
V
PWM
= 3.3V
V
PWM
= 0V
PWM Rising Threshold (Note 4)
PWM Falling Threshold (Note 4)
Typical Three-State Shutdown Window
Three-State Lower Gate Falling Threshold
Three-State Lower Gate Rising Threshold
Three-State Upper Gate Rising Threshold
Three-State Upper Gate Falling Threshold
Shutdown Hold-off Time
UGATE Rise Time (Note 4)
LGATE Rise Time (Note 4)
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-On Propagation Delay (Note 4)
t
TSSHD
t
RU
t
RL
t
FU
t
FL
t
PDHU
V
PVCC
= 12V, 3nF Load, 10% to 90%
V
PVCC
= 12V, 3nF Load, 10% to 90%
V
PVCC
= 12V, 3nF Load, 90% to 10%
V
PVCC
= 12V, 3nF Load, 90% to 10%
V
PVCC
= 12V, 3nF Load, Adaptive
V
CC
= 12V
V
CC
= 12V
V
CC
= 12V
V
CC
= 12V
V
CC
= 12V
V
CC
= 12V
V
CC
= 12V
-
-
-
-
1.23
-
-
-
-
-
-
-
-
-
-
400
-350
1.70
1.30
-
1.18
0.76
2.36
1.96
245
26
18
18
12
10
-
-
-
-
1.82
-
-
-
-
-
-
-
-
-
-
µA
µA
V
V
V
V
V
V
V
ns
ns
ns
ns
ns
ns
6.1
4.7
6.4
5.0
6.7
5.3
V
V
FN9282 Rev 1.00
Dec 3, 2007
Page 4 of 11
ISL6594D
Electrical Specifications
PARAMETER
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Three-State Propagation Delay (Note 4)
OUTPUT (Note 4)
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
Lower Drive Sink Impedance
NOTE:
4. Limits should be considered typical and are not production tested.
I
U_SOURCE
V
PVCC
= 12V, 3nF Load
R
U_SOURCE
150mA Source Current
I
U_SINK
R
U_SINK
I
L_SOURCE
V
PVCC
= 12V, 3nF Load
150mA Sink Current
V
PVCC
= 12V, 3nF Load
-
1.4
-
0.9
-
0.85
-
0.60
1.25
2.0
2
1.65
2
1.3
3
0.94
-
3.0
-
3.0
-
2.2
-
1.35
A
A
A
A
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
SYMBOL
t
PDHL
t
PDLU
t
PDLL
t
PDTS
TEST CONDITIONS
V
PVCC
= 12V, 3nF Load, Adaptive
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
MIN
-
-
-
-
TYP
10
10
10
10
MAX
-
-
-
-
UNITS
ns
ns
ns
ns
R
L_SOURCE
150mA Source Current
I
L_SINK
R
L_SINK
V
PVCC
= 12V, 3nF Load
150mA Sink Current
Functional Pin Description
PACKAGE PIN #
SOIC
1
2
DFN
1
2
PIN
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal
Bootstrap
Device”
on page 7 for guidance in choosing the capacitor value.
No Connection.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
“Three-State
PWM Input”
on page 6 for further details. Connect this pin to the PWM output of the controller.
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high
quality low ESR ceramic capacitor from this pin to GND.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
-
3
4
5
6
7
8
9
3, 8
4
5
6
7
9
10
11
N/C
PWM
GND
LGATE
VCC
PVCC
PHASE
PAD
FN9282 Rev 1.00
Dec 3, 2007
Page 5 of 11
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
